45nm低功耗CMOS高k栅极堆叠的单金属栅极

2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI:10.1109/IEDM.2006.346861

W. Taylor, C. Capasso, B. Min, B. Winstead, E. Verret, K. Loiko, D. Gilmer, R. Hegde, J. Schaeffer, E. Luckowski, A. Martínez, M. Raymond, C. Happ, D. Triyoso, S. Kalpat, A. Haggag, D. Roan, J. Nguyen, L. La, L. Hebert, J. Smith, D. Jovanovic, D. Burnett, M. Foisy, N. Cave, P. Tobin, S. Samavedam, S. B. White, S. Venkatesan

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引用次数: 3

摘要

我们提出了一种低成本的单金属栅极/高k栅极堆叠集成，它为45nm低功耗(LP) CMOS技术提供了一个非常高性能的NMOS和反掺杂PMOS。反转Tox (Tinv)值为16Aring/18Aring (NMOS/PMOS)导致栅极泄漏电流密度为0.1/0.01 A/ cm2，并使自热驱动电流为850/325muA/mum，在1nA/mum的断开状态泄漏和Vdd=1V (900/340muA/mum非自热)。此外，在Ioff = 100nA/mum和Vdd=1.2V时，NMOS驱动电流为1550 muA/mum(非自热1650muA/mum)，这是基于铪的高k栅极堆栈的最高报道。该方法与用于I/O设备的双栅氧化物(DGO)模块兼容，并允许优化性能和功耗，通常只有在三栅氧化物架构中才有可能实现

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Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS

We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion Tox (Tinv) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and Vdd=1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an Ioff = 100nA/mum and Vdd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures

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2006 International Electron Devices Meeting

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