Soon-Moon Jung, J. Jang, W. Cho, Hoosung Cho, Jaehun Jeong, Youngchul Chang, Jonghyuk Kim Youngseop Rah, Y. Son, Junbeom Park, Minsung Song, Kyoung-Hoon Kim, Jm-Soo Lim, Kinam Kim
{"title":"Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node","authors":"Soon-Moon Jung, J. Jang, W. Cho, Hoosung Cho, Jaehun Jeong, Youngchul Chang, Jonghyuk Kim Youngseop Rah, Y. Son, Junbeom Park, Minsung Song, Kyoung-Hoon Kim, Jm-Soo Lim, Kinam Kim","doi":"10.1109/IEDM.2006.346902","DOIUrl":null,"url":null,"abstract":"For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on the bulk to double the memory density without increasing the chip size. The feasibility of the technology was proven by the successful operation of 32 bit NAND flash memory cell strings with 63nm dimension and TANOS structures. The novel NAND cell operational scheme, so called SBT (source-body tied) scheme, is presented to maximize the advantages of 3 dimensionally stacked NAND cell structures","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"107","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346902","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 107
Abstract
For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on the bulk to double the memory density without increasing the chip size. The feasibility of the technology was proven by the successful operation of 32 bit NAND flash memory cell strings with 63nm dimension and TANOS structures. The novel NAND cell operational scheme, so called SBT (source-body tied) scheme, is presented to maximize the advantages of 3 dimensionally stacked NAND cell structures
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
