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2016 IEEE 8th International Memory Workshop (IMW)最新文献

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Analytical Model to Evaluate the Role of Deep Trap State in the Reliability of NAND Flash Memory and Its Process Dependence 深阱状态对NAND闪存可靠性影响的分析模型及其工艺依赖性
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493567
B-J Yang, Y-T Wu, Y. Chiu, R. Shirota, T.-M. Kuo, J. Chang, P-Y Wang
{"title":"Analytical Model to Evaluate the Role of Deep Trap State in the Reliability of NAND Flash Memory and Its Process Dependence","authors":"B-J Yang, Y-T Wu, Y. Chiu, R. Shirota, T.-M. Kuo, J. Chang, P-Y Wang","doi":"10.1109/IMW.2016.7493567","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493567","url":null,"abstract":"An elementary step of trap and detrap processes of electron in the tunnel oxide during program/erase in NAND Flash memory is precisely studied. Owing to the high electric field during program and erase (P/E), the electron trapping and detrapping occur at the same time. Consequently, the detrapping process only leaves electrons in the deeper trap energy state (Etrap) than 3.5 eV. In addition, as-grown trap density (Ne) and capture cross section (σ) in the deep trap state can be specified to explain the measured data including the tunneling current modulation with cycling and the VT shift by oxide trap. The P/E endurance characteristics using dry and plasma oxidation processes are analyzed and compared. In both processes, σ has the same value (~4 × 10-17 cm2). However, Ne depends on the oxidation process. In dry oxidation, Ne is ~1.88 × 1019 cm-3. On the other hand, in plasma oxidation, 30% reduction (~1.25 × 1019 cm-3) can be found.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115181327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Privacy-Protection SSD with Precision ECC and Crush Techniques for 15.5× Improved Data-Lifetime Control 具有精密ECC和粉碎技术的隐私保护SSD，用于15.5倍改进的数据寿命控制
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495286
Hiroki Yamazawa, Kazuki Maeda, Tomoko Ogura Iwasaki, K. Takeuchi
{"title":"Privacy-Protection SSD with Precision ECC and Crush Techniques for 15.5× Improved Data-Lifetime Control","authors":"Hiroki Yamazawa, Kazuki Maeda, Tomoko Ogura Iwasaki, K. Takeuchi","doi":"10.1109/IMW.2016.7495286","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495286","url":null,"abstract":"The privacy-protection solid-state storage (PP-SSS) system is a proposal for Internet-data's \"right to be forgotten\", in which data-lifetimes are specified without file-system overhead. In NAND flash memory, the data-lifetimes are controlled by intentionally injecting errors into the data during write, to accelerate retention failure. However, the previously reported PP-SSS [1] has 2 issues, wide variation of data-lifetime and limited effectiveness for uncompressed data. In this work, based on 1Xnm TLC NAND flash measurement, 2 improvement techniques are demonstrated. Precision ECC increases the ECC codeword length and crush judges when the data expires and converts it to black/ irrecoverable data. When precision ECC and crush are applied to conventional PP-SSS, data-lifetime variation decreases by 15.5×, from 31 days to 2 days, and both compressed and uncompressed data can be protected.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"54 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123654416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High Operating Temperature Reliability of Optimized Ge-Rich GST Wall PCM Devices 优化的富锗GST壁型PCM器件的高温可靠性
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495273
J. Kluge, G. Navarro, V. Sousa, N. Castellani, S. Blonkowski, R. Annunziata, P. Zuliani, L. Perniola
{"title":"High Operating Temperature Reliability of Optimized Ge-Rich GST Wall PCM Devices","authors":"J. Kluge, G. Navarro, V. Sousa, N. Castellani, S. Blonkowski, R. Annunziata, P. Zuliani, L. Perniola","doi":"10.1109/IMW.2016.7495273","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495273","url":null,"abstract":"The reliability of optimized Ge-rich GST \"Wall\" Phase Change Memory (PCM) devices is investigated at high operating temperatures. Endurance of more than 107 cycles is ensured up to 175 °C. A cell thermal resistance 45% higher wrt standard GST devices is demonstrated, granting reduced cell to cell thermal crosstalk. Increased temperatures show to have a limited impact on the programming speed. Finally, specific programming sequences are proposed to reduce the drift of intermediate resistance states at high temperature.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133210258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
In Depth Analysis of Post-Program VT Instability after Electrical Stress in 3D SONOS Memories 三维SONOS记忆体电应力后编程后VT不稳定性的深入分析
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495278
A. Subirats, A. Arreghini, R. Degraeve, D. Linten, G. Van den bosch, A. Furnémont
{"title":"In Depth Analysis of Post-Program VT Instability after Electrical Stress in 3D SONOS Memories","authors":"A. Subirats, A. Arreghini, R. Degraeve, D. Linten, G. Van den bosch, A. Furnémont","doi":"10.1109/IMW.2016.7495278","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495278","url":null,"abstract":"Through Post-Program-Discharge measurements we achieve in-depth understanding of the ONO stack degradation observed in 3D SONOS memories that results in VT instabilities after the program pulse. We demonstrate that hole injection during erase is degrading the Tunnel Oxide, leading to formation of defects, that can be charged during program but emit electrons soon after. Through device simulations, we could also achieve a precise profiling in space and energy of these stress-generated SiO2 defects and develop a complete model of charge loss in degraded devices.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"121 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121188101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip 利用2mbit 1T-1MTJ STT-MRAM测试芯片演示On-Via MTJ成品率的提高
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495264
H. Koike, S. Miura, H. Honjo, Toshinari Watanabe, Hideo Sato, S. Sato, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, M. Muraguchi, M. Niwa, Kenchi Ito, S. Ikeda, H. Ohno, T. Endoh
{"title":"Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip","authors":"H. Koike, S. Miura, H. Honjo, Toshinari Watanabe, Hideo Sato, S. Sato, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, M. Muraguchi, M. Niwa, Kenchi Ito, S. Ikeda, H. Ohno, T. Endoh","doi":"10.1109/IMW.2016.7495264","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495264","url":null,"abstract":"To realize a high-density spin-transfer-torque magnetic random access memory (STT-MRAM) device comparable with a current dynamic random access memory (DRAM) device, it is a key to develop a new technology for memory cell size reduction. We have already reported a chemical- mechanical-polishing(CMP)-based preparation technology for magnetic tunnel junctions (MTJs) above the via holes that can drastically reduce memory cell area. In this paper, we first introduce the MTJ preparation technology to the mega-bit class STT-MRAM test chip, and demonstrate the improvement of memory-cell operation yield.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116878068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An Efficient Sudden-Power-Off-Recovery Design with Guaranteed Booting Time for Solid State Drives 一个有效的突然断电恢复设计与保证启动时间的固态驱动器
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493565
Yu-Ming Chang, P. Lin, Ye-Jyun Lin, T. Kuo, Yuan-Hao Chang, Yung-Chun Li, Hsiang-Pang Li, K. C. Wang
{"title":"An Efficient Sudden-Power-Off-Recovery Design with Guaranteed Booting Time for Solid State Drives","authors":"Yu-Ming Chang, P. Lin, Ye-Jyun Lin, T. Kuo, Yuan-Hao Chang, Yung-Chun Li, Hsiang-Pang Li, K. C. Wang","doi":"10.1109/IMW.2016.7493565","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493565","url":null,"abstract":"Solid state drives (SSDs) that deliver high- bandwidth and low-latency performance have become the mainstream of storage devices in modern systems. Over the past years, there has been a great deal of researches conducted to improve the SSD performance or reliability with parallel or efficient address translation designs. On the contrary, little work is done for the optimization to guarantee the booting/recovery time of SSDs after any sudden power-off. Motivated by the fact that the fast-growing SSD capacity gradually makes existing scanning and recovering processes become infeasible and unacceptable, we propose an efficient sudden-power-off-recovery design to recover an SSD with guaranteed booting time. The proposed design was implemented on an SSD prototyping platform equipped with in-house NAND flash memories and was evaluated with various benchmarks. The results demonstrate that after sudden power-off, the prototyped SSD can be recovered with a guaranteed and bounded booting time between 80ms and 200ms.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122164046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Investigation of Factors Affecting SET-Disturb Failure Time in a Resistive Switching Memory
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495281
P. Su, Y. T. Chung, M. C. Chen, Tahui Wang
{"title":"Investigation of Factors Affecting SET-Disturb Failure Time in a Resistive Switching Memory","authors":"P. Su, Y. T. Chung, M. C. Chen, Tahui Wang","doi":"10.1109/IMW.2016.7495281","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495281","url":null,"abstract":"Factors affecting SET-disturb failure time (τf) in a tungsten oxide resistive switching memory including SET/RESET cycling stress, resistance window in operation and SET-disturb voltage are investigated. A SET-disturb failure time in high resistance state (HRS) may degrade by orders of magnitude in a post-cycling cell. The degradation is attributed to the formation of a current percolation path of cycling stress-generated traps. A one-dimensional percolation model is proposed for the τf degradation. The dependence of τf on resistance window in operation is characterized. We find that τf is greatly affected by the current level of LRS. The strong LRS dependence of τf is attributed to a small Weibull slope of τf. In addition, we perform statistical characterizations of τf at different SET-disturb voltages. A relationship between τf and a SET-disturb voltage in a stressed cell is given.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127029348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fully Analytical Compact Model of OxRAM Based on Joule Heating and Electromigration for DC and Pulsed Operation 基于焦耳加热和电迁移的直流和脉冲工作OxRAM全解析紧凑模型
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495270
S. Blonkowski, T. Cabout, M. Azazz, C. Cagli, E. Jalaguier
{"title":"Fully Analytical Compact Model of OxRAM Based on Joule Heating and Electromigration for DC and Pulsed Operation","authors":"S. Blonkowski, T. Cabout, M. Azazz, C. Cagli, E. Jalaguier","doi":"10.1109/IMW.2016.7495270","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495270","url":null,"abstract":"A totally analytic compact model of bipolar switching in oxide based resistive memory is reported. Analytical expressions reproducing the switching in the case of ramp voltage and short voltage pulses without any iterative procedure are given. The model results are compared to experimental data and to a numerical model containing the same physical basis.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115456700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Statistical Evaluation of Correlations between LRS and HRS Relaxations in RRAM Array RRAM阵列中LRS和HRS弛豫相关性的统计评价
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495291
Chen Wang, Huaqiang Wu, B. Gao, Lingjun Dai, Dong Wu, H. Qian, D. Sekar, Zhichao Lu, G. Bronner
{"title":"The Statistical Evaluation of Correlations between LRS and HRS Relaxations in RRAM Array","authors":"Chen Wang, Huaqiang Wu, B. Gao, Lingjun Dai, Dong Wu, H. Qian, D. Sekar, Zhichao Lu, G. Bronner","doi":"10.1109/IMW.2016.7495291","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495291","url":null,"abstract":"The unique tail bits retention failure behavior is observed in the RRAM array. Unlike the previous reports on single device or the average value''s retention behavior, quick retention loss of tail bits is found for both LRS and HRS. By statistically characterized such relaxation effect of tail bits, physical models are built to quantitatively describe the relaxation behaviors of LRS and HRS. The correlation between LRS and HRS relaxations is explored. Interfacial migration of oxygen ions is clarified to be the possible reason for the relaxation, which can provide the basis of the optimization of retention properties in RRAM array.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124584786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Carbon-Based Resistive Memories 碳基电阻存储器
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493569
W. Koelmans, T. Bachmann, F. Zipoli, A. Ott, C. Dou, A. Ferrari, O. Cojocaru-Mirédin, S. Zhang, C. Scheu, M. Wuttig, V. K. Nagareddy, M. Craciun, A. Alexeev, C. Wright, V. Jonnalagadda, A. Curioni, A. Sebastian, E. Eleftheriou
{"title":"Carbon-Based Resistive Memories","authors":"W. Koelmans, T. Bachmann, F. Zipoli, A. Ott, C. Dou, A. Ferrari, O. Cojocaru-Mirédin, S. Zhang, C. Scheu, M. Wuttig, V. K. Nagareddy, M. Craciun, A. Alexeev, C. Wright, V. Jonnalagadda, A. Curioni, A. Sebastian, E. Eleftheriou","doi":"10.1109/IMW.2016.7493569","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493569","url":null,"abstract":"Carbon-based nonvolatile resistive memories are an emerging technology. Switching endurance remains a challenge in carbon memories based on tetrahedral amorphous carbon (ta-C). One way to counter this is by oxygenation to increase the repeatability of reversible switching. Here, we overview the current status of carbon memories. We then present a comparative study of oxygen-free and oxygenated carbon-based memory devices, combining experiments and molecular dynamics (MD) simulations.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124195598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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