2016 IEEE 8th International Memory Workshop (IMW)最新文献

N-Doping Impact in Optimized Ge-Rich Materials Based Phase-Change Memory n掺杂对优化富锗材料相变存储器的影响

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-06-23 DOI: 10.1109/IMW.2016.7495284

G. Navarro, V. Sousa, P. Noé, N. Castellani, M. Coue, J. Kluge, A. Kiouseloglou, C. Sabbione, A. Persico, A. Roule, O. Cueto, S. Blonkowski, F. Fillot, N. Bernier, R. Annunziata, M. Borghi, E. Palumbo, P. Zuliani, L. Perniola

引用次数: 10

Hybrid CMOS-OxRAM Image Sensor for Overexposure Control 用于过度曝光控制的CMOS-OxRAM混合图像传感器

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495276

A.Sai Kumar, M. Sarkar, M. Suri

引用次数: 5

Theoretical Analysis of Planar Flat Floating Gate NAND Flash Device and Experimental Study of Floating-Gate (FG) / Charge-Trapping (CT) Fusion Device for Comprehensive Understanding of Charge Storage and Operation Principle 平面扁平浮栅NAND闪存器件的理论分析和浮栅/电荷俘获融合器件的实验研究，全面理解电荷存储和工作原理

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495292

H. Lue, P. Du, R. Lo, Chih-Yuan Lu

{"title":"Theoretical Analysis of Planar Flat Floating Gate NAND Flash Device and Experimental Study of Floating-Gate (FG) / Charge-Trapping (CT) Fusion Device for Comprehensive Understanding of Charge Storage and Operation Principle","authors":"H. Lue, P. Du, R. Lo, Chih-Yuan Lu","doi":"10.1109/IMW.2016.7495292","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495292","url":null,"abstract":"The planar flat FG device is theoretically studied extensively. There is a puzzle whether the charge is stored in the inter gate dielectric (IGD). A planar cell has no geometrical coupling ratio help thus IGD bears very high E-field. A high work function FG together with a robust interfacial layer between FG and high-K material that has both large barrier height and large dielectric constant are needed to reduce the out tunneling current. Thus our detailed tunneling simulation indicates that to obtain an “ideal planar FG” device with a large memory window but without charge-trapping in IGD is quite challenging. On the other hand, a very interesting finding from our simulation is that the opposite scenario assuming charge trapping in IGD can also provide identical ISPP/ISPE characteristic as the ideal FG device. This leads to a paradox (Rashomon) for a correct theoretical model for the device. In order to solve this paradox, we propose to apply a gate-sensing and channel-sensing (GSCS) technique to detect the charge location and dig out the real answer of operation principle. GSCS study of FG SONOS “Fusion” device shows that in a device that has both FG and trapping IGD the FG holds only limited amount of electrons and most electrons are stored in the IGD. Finally, the FG/CT fusion devices of the planar FG SONOS and FG BE-SONOS (without high-K and metal gate) are experimentally studied. They show very large memory window (>16V) with nearly ideal ISPP/ISPE slope ~1.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124718080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Construction of High-Rate Generalized Concatenated Codes for Applications in Non-Volatile Flash Memories 用于非易失性闪存的高速率广义级联码的构造

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493571

Jens Spinner, Mohammed Rajab, J. Freudenberger

引用次数: 13

Vertical CBRAM (V-CBRAM): From Experimental Data to Design Perspectives 垂直CBRAM (V-CBRAM):从实验数据到设计视角

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495296

G. Piccolboni, M. Parise, G. Molas, A. Levisse, J. Portal, R. Coquand, C. Carabasse, M. Bernard, A. Roule, J. Noel, B. Giraud, M. Harrand, C. Cagli, T. Magis, E. Vianello, B. De Salvo, G. Ghibaudo, L. Perniola

引用次数: 6

17x Reliability Enhanced LDPC Code with Burst-Error Masking and High-Precision LLR for Highly Reliable Solid-State-Drives with TLC NAND Flash Memory 17x可靠性增强LDPC码与突发错误掩蔽和高精度LLR高可靠的固态驱动器与TLC NAND闪存

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493561

Tsukasa Tokutomi, K. Takeuchi

引用次数: 2

Endurance/Retention Trade Off in HfOx and TaOx Based RRAM 基于HfOx和TaOx的RRAM的持久性/留存率权衡

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495268

M. Azzaz, E. Vianello, B. Sklénard, P. Blaise, A. Roule, C. Sabbione, S. Bernasconi, C. Charpin, C. Cagli, E. Jalaguier, S. Jeannot, S. Denorme, P. Candelier, M. Yu, L. Nistor, C. Fenouillet-Béranger, L. Perniola

引用次数: 26

Highly Scalable 2nd-Generation 45-nm Split-Gate Embedded Flash with 10-ns Access Time and 1M-Cycling Endurance 高度可扩展的第二代45纳米分闸嵌入式闪存，具有10ns访问时间和1m循环续航时间

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495275

Yong Kyu Lee, Hongkook Min, Changmin Jeon, B. Seo, Gayoung Lee, Eunkang Park, Donghyun Kim, Changhyun Park, B. Kwon, Minsu Kim, Bongsang Lee, Duckhyung Lee, Hyosang Lee, Jisung Kim, Sunghee Cho

引用次数: 2

Application Optimized Adaptive ECC with Advanced LDPCs to Resolve Trade-Off among Reliability, Performance, and Cost of Solid-State Drives 应用优化自适应ECC与先进ldpc解决可靠性，性能和成本之间的权衡固态驱动器

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493568

Y. Yamaga, C. Matsui, Shogo Hachiya, K. Takeuchi

{"title":"Application Optimized Adaptive ECC with Advanced LDPCs to Resolve Trade-Off among Reliability, Performance, and Cost of Solid-State Drives","authors":"Y. Yamaga, C. Matsui, Shogo Hachiya, K. Takeuchi","doi":"10.1109/IMW.2016.7493568","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493568","url":null,"abstract":"The performance of NAND flash based solid-state drives (SSDs) is highly dependent on the application's read and write characteristics [3], where \"intensity\" is defined as ratio of read:write requests, and \"write- hot/cold\" considers the write frequency. Moreover, NAND flash memory's reliability degrades with write/erase (W/E) cycling. To optimize performance and reliability, conventional error-correcting code (ECC) scheme switches from fast conventional Bose-Chaudhuri- Hocquenghem (BCH) to slower conventional Low Density Parity Check (LDPC), when the page error rate exceeds BCH's decoding capability. However, advanced LDPCs have been reported, called Quick-LDPC [8] and Error- Prediction (EP-) LDPC without (w/o) upper/lower cells [8], which have (i) higher error correction capability compared to conventional BCH and (ii) shorter decoding time than conventional soft-decoding LDPC. Therefore, this paper proposes an application optimized adaptive (AOA-) ECC for Multi-Level-Cell (MLC) NAND flash-based enterprise SSDs. AOA-ECC includes a new algorithm to efficiently combine the two advanced LDPCs, considering the application's characteristics and memory's W/E cycles. A firmware in the proposed SSD system chooses the optimal advanced LDPC, based on whether the application is read/write-intensive and/or write- hot/cold. Using the proposed AOA-ECC SSD with MLC NAND flash, performance improves by up to 3-times, the reliability improves by 57% and the ECC decoder area decreases by 25%.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D NAND Flash Architecture and Studies of Bottom Source Engineering 一种底源单栅垂直通道(BS-SGVC) 3D NAND闪存架构及底源工程研究

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493562

S. Lai, H. Lue, T. Hsu, C. Wu, Li-yang Liang, P. Du, C. Chiu, Chih-Yuan Lu

{"title":"A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D NAND Flash Architecture and Studies of Bottom Source Engineering","authors":"S. Lai, H. Lue, T. Hsu, C. Wu, Li-yang Liang, P. Du, C. Chiu, Chih-Yuan Lu","doi":"10.1109/IMW.2016.7493562","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493562","url":null,"abstract":"Vertical channel (VC) 3D NAND Flash may be categorized into two types of channel formation: (1) \"U-turn\" string, where both BL and source are connected at top thus channel current flows in a U-turn way; (2) \"Bottom source\", where source is connected at the bottom thus channel current flows only in one way. For the single-gate vertical channel (SGVC) 3D NAND architecture [1], it is also possible to develop a bottom source structure. The detailed array decoding method is illustrated. In this work, the challenges of bottom source processing and thin poly channel formation are extensively studied. It is found that the two-step poly formation and the bottom recess control are two key factors governing the device initial performance. In general, the two-step poly formation with additional poly spacer etching technique seems to cause degradation of both the poly mobility and device subthreshold slope. Sufficient thermal annealing is needed to recover the damage. Moreover, the bottom connection needs an elegant recess control for better read current as well as bottom ground-select transistor (GSL) device optimizations.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"12 1-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134231596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5