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In-Depth Analysis of NBTI at 2X nm Node DRAM 2X nm节点DRAM的NBTI深度分析
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495279
S. Han, Sungsam Lee, S. Baek, S. Jang, W. Jeong, K. Huh, Moonyoung Jeong, Junhee Lim, S. Yamada, H. Hong, Kyupil Lee, Gyoyoung Jin, E. Jung
{"title":"In-Depth Analysis of NBTI at 2X nm Node DRAM","authors":"S. Han, Sungsam Lee, S. Baek, S. Jang, W. Jeong, K. Huh, Moonyoung Jeong, Junhee Lim, S. Yamada, H. Hong, Kyupil Lee, Gyoyoung Jin, E. Jung","doi":"10.1109/IMW.2016.7495279","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495279","url":null,"abstract":"An analysis on the degradation of DRAM performance caused by the NBTI degradation of p-MOSFET is first to be reported. To improve the NBTI immunity, three candidates are examined. First, minimizing Si-H bonds at Si/SiON interface through controlling the heat-budget at BEOL shows a promising result in NBTI lifetime, but it is not appropriate for DRAM process since it decreases the refresh time. Next, the buried SiGe channel p-MOSFET, which has 1.2 times higher NBTI immunity, is considered but difficult to adopt in DRAM peripheral circuit due to extra manufacturing cost. Finally, a deuterium annealing seems to be the right candidate for DRAM process since it improves the NBTI immunity without the refresh time penalty. This NBTI gain, however, varies depending on the amount of deuterium atom at Si/SiON interface and the probability of Si-D bond replacement with Si-H bond. Thus, selecting a right process sequence and an annealing condition is crucial.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"36 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133148048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Universal Signatures from Non-Universal Memories: Clues for the Future... 来自非普遍记忆的普遍特征:未来的线索……
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495295
L. Perniola, G. Molas, G. Navarro, E. Nowak, V. Sousa, E. Vianello, B. De Salvo
{"title":"Universal Signatures from Non-Universal Memories: Clues for the Future...","authors":"L. Perniola, G. Molas, G. Navarro, E. Nowak, V. Sousa, E. Vianello, B. De Salvo","doi":"10.1109/IMW.2016.7495295","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495295","url":null,"abstract":"The quest for the universal memory has been pursued since several years, but as far results from scientific literature do not declare one single technology able to fit all the requirements of the memory hierarchy. Flash and DRAM cover more than 95% of the global sales in the semiconductor memory market [1], but none of the two is able to substitute the other. This appears to be true also for disruptive backend memory technologies, like OxRAM, CBRAM, PCM and MRAM. This paper deals with universal signatures that stand true for such disruptive technologies. A specific analysis on two case examples from the RRAM and the PCM domain, where tradeoffs can be adjusted to target specific applications, is finally proposed. Knowing in advance the tradeoffs of each technology allows us to save precious time in research and development and therefore to accelerate the time-to-market.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126128565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An Ultra Low-Power Non-Volatile Memory Design Enabled by Subquantum Conductive-Bridge RAM 基于亚量子电导桥RAM的超低功耗非易失性存储器设计
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493566
Nathan Gonzales, J. Dinh, D. Lewis, N. Gilbert, Bard Pedersen, D. Kamalanathan, J. Jameson, S. Hollmer
{"title":"An Ultra Low-Power Non-Volatile Memory Design Enabled by Subquantum Conductive-Bridge RAM","authors":"Nathan Gonzales, J. Dinh, D. Lewis, N. Gilbert, Bard Pedersen, D. Kamalanathan, J. Jameson, S. Hollmer","doi":"10.1109/IMW.2016.7493566","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493566","url":null,"abstract":"Conductive-bridge RAM (CBRAM) memory cells offer speed, voltage, and energy advantages over floating gate flash cells. Here, we describe a memory design which carries these cell-level advantages up to the product level, achieving 100x lower read and write power and 10x lower standby power than typical flash-based designs.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131305188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM 在DRAM中使用双工作功能金属栅极降低GIDL
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495287
S. K. Gautam, S. Maheshwaram, S. Manhas, Arvind Kumar, S. Sherman, S. Jo
{"title":"Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM","authors":"S. K. Gautam, S. Maheshwaram, S. Manhas, Arvind Kumar, S. Sherman, S. Jo","doi":"10.1109/IMW.2016.7495287","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495287","url":null,"abstract":"A novel work-function modulation technique for dual work-function (WF) metal gate for DRAM access device is investigated to minimize the leakage current in the access transistor. Gate Induced Drain Leakage (GIDL) is believed to be the most dominant off state leakage from storage node junction. Due to high doping in access device storage node side, lateral electric field near the storage node increases, which enhance the GIDL. Increased GIDL in DRAM puts limits on further scaling of DRAM cell. In this paper GIDL current dependence on gate metal work function has been investigated with TCAD simulation. A solution is proposed to minimize the GIDL current as well as possible fabrication techniques.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134257544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Comparative Analysis of Program/Read Disturb Robustness for GeSbTe-Based Phase-Change Memory Devices 基于gesbte的相变存储器件的程序/读干扰鲁棒性比较分析
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493570
N. Castellani, G. Navarro, V. Sousa, P. Zuliani, R. Annunziata, M. Borghi, L. Perniola, G. Reimbold
{"title":"Comparative Analysis of Program/Read Disturb Robustness for GeSbTe-Based Phase-Change Memory Devices","authors":"N. Castellani, G. Navarro, V. Sousa, P. Zuliani, R. Annunziata, M. Borghi, L. Perniola, G. Reimbold","doi":"10.1109/IMW.2016.7493570","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493570","url":null,"abstract":"We propose a comparative analysis for Ge2Sb2Te5 (GST) and Ge-rich GST based Phase-Change Memory (PCM) devices in terms of program/read disturbs robustness. We present the characterization of the intrinsic drift of the materials, the investigation of the devices response to electrical stress and, finally, the study of the PCM cell behavior in extreme disturb conditions. A higher immunity for Ge-rich GST is verified as well as the importance of high-resistance drift as inhibitor for sub-threshold switching phenomenon.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128456754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Internal Cell Resistance as the Origin of Abrupt Reset Behavior in HfO2-Based Devices Determined from Current Compliance Series 电池内部电阻是基于hfo2的器件中突然复位行为的起源，由电流依从性系列确定
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495280
A. Hardtdegen, Camilla La Torre, Hehe Zhang, C. Funck, S. Menzel, R. Waser, S. Hoffmann‐Eifert
{"title":"Internal Cell Resistance as the Origin of Abrupt Reset Behavior in HfO2-Based Devices Determined from Current Compliance Series","authors":"A. Hardtdegen, Camilla La Torre, Hehe Zhang, C. Funck, S. Menzel, R. Waser, S. Hoffmann‐Eifert","doi":"10.1109/IMW.2016.7495280","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495280","url":null,"abstract":"The resistive switching behavior in different HfO2/TiO2 nano crossbar structures of 100 x 100 nm2 size is analyzed by means of DC voltage sweeps. The devices fabricated from 3 nm thin ALD layers of HfO2 and TiO2 sandwiched between Pt and Hf or Ti electrodes show VCM-type bipolar resistive switching after electroforming. For increased compliance current (cc) during set from 50 μA to 800 μA, the set current runs into self- limitation while the reset behavior changes from gradual to abrupt. A model is defined with an internal resistance being in series with the local resistive switch. A recursive algorithm is applied to the cc series for calculation of the series resistor and evaluation of the intrinsic switching characteristic of HfO2-based cells. The intrinsic LRS turns out to be current compliance controlled and to follow the universal switching rule. Supported by compact modelling, we show that an abrupt reset behavior might arise even for materials with a gradual intrinsic reset characteristic in consequence of an internal series resistor.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127124955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Control of Sub-Nanosecond Precessional Magnetic Switching in STT-MRAM Cells for SRAM Applications 用于SRAM的STT-MRAM单元的亚纳秒进动磁开关控制
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495262
B. Lacoste, M. Marins de Castro, R. Sousa, I. Prejbeanu, L. Buda-Prejbeanu, S. Auffret, U. Ebels, B. Rodmacq, B. Dieny
{"title":"Control of Sub-Nanosecond Precessional Magnetic Switching in STT-MRAM Cells for SRAM Applications","authors":"B. Lacoste, M. Marins de Castro, R. Sousa, I. Prejbeanu, L. Buda-Prejbeanu, S. Auffret, U. Ebels, B. Rodmacq, B. Dieny","doi":"10.1109/IMW.2016.7495262","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495262","url":null,"abstract":"STT-MRAM are foreseen as the best contender for DRAM replacement. STT-MRAM could also be used for SRAM applications if switching time below 1ns could be realized in a reliable way. In this study, we demonstrate that sub-ns switching with final state determined by the current polarity through the stack can be achieved in STT-MRAM cells comprising two spin-polarizing layers having orthogonal magnetic anisotropies [1],[2]. We carried out a thorough experimental and modeling study of these ultrafast STT-MRAM. We demonstrated that a quite reliable switching can be achieved by increasing the cell aspect ratio (AR) or advantageously by applying an in-plane static transverse field on the cell. Switching in 200ps could be demonstrated with write energy less than 100fJ.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134538577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications 一种具有533MB/s读写速率和37.5ns访问延迟的双数据速率2 (DDR2)接口相变存储器
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493563
H. Lung, Christopher P. Miller, Chia-Jung Chen, S. Lewis, J. Morrish, T. Perri, R. Jordan, H. Ho, T. Chen, W. Chien, Mark Drapa, T. Maffitt, J. Heath, Yutaka Nakamura, J. Okazawa, K. Hosokawa, M. BrightSky, R. Bruce, Huai-Yu Cheng, A. Ray, Y. Ho, C. Yeh, Wanki Kim, Sangbum Kim, Yu Zhu, C. Lam
{"title":"A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications","authors":"H. Lung, Christopher P. Miller, Chia-Jung Chen, S. Lewis, J. Morrish, T. Perri, R. Jordan, H. Ho, T. Chen, W. Chien, Mark Drapa, T. Maffitt, J. Heath, Yutaka Nakamura, J. Okazawa, K. Hosokawa, M. BrightSky, R. Bruce, Huai-Yu Cheng, A. Ray, Y. Ho, C. Yeh, Wanki Kim, Sangbum Kim, Yu Zhu, C. Lam","doi":"10.1109/IMW.2016.7493563","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493563","url":null,"abstract":"For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115629380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Heirarchical Full-Chip Fast-Simulation Based Design Mitigation of CHC in NAND Flash Memory 基于分层全片快速仿真的NAND闪存CHC缓解设计
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495272
B. Vaidyanathan, P. Kauk, S. Krishnan, M. Advani, Qiang Tang, Mattia Cichocki, M. Tiburzi, M. Incarnati
{"title":"Heirarchical Full-Chip Fast-Simulation Based Design Mitigation of CHC in NAND Flash Memory","authors":"B. Vaidyanathan, P. Kauk, S. Krishnan, M. Advani, Qiang Tang, Mattia Cichocki, M. Tiburzi, M. Incarnati","doi":"10.1109/IMW.2016.7495272","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495272","url":null,"abstract":"Industry-standard Circuit Reliability simulation Tools (ICRT) to simulate Channel Hot Carrier (CHC) is either not possible at the full-chip level consisting of few million transistors or time consuming and prone to abrupt termination of simulation due to resource usage anomalies at reasonable large sub-block level. We have proposed a hierarchical design-in-reliability methodology to identify CHC aging of critical transistors accurately at full-chip level in 10x faster time than required by ICRT. Accurate reliability simulation and design mitigation is later carried out at much smaller and critical sub-block level using ICRT. We have demonstrated our methodology in screening critical blocks in a NAND flash memory and the results are provided thus enabling reliable and faster time to tape-out.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132486226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Threshold Switching in Amorphous Cr-Doped Vanadium Oxide for New Crossbar Selector 新型横杆选择器中非晶态掺cr氧化钒的阈值开关
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495293
J. Rupp, R. Waser, D. Wouters
{"title":"Threshold Switching in Amorphous Cr-Doped Vanadium Oxide for New Crossbar Selector","authors":"J. Rupp, R. Waser, D. Wouters","doi":"10.1109/IMW.2016.7495293","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495293","url":null,"abstract":"Symmetrical (Pt) electroded undoped (Pt/a-VO<sub>x</sub>/Pt) and Cr-doped amorphous Vanadium Oxide (Pt/a-V<sub>1-y</sub>Cr<sub>y</sub>O<sub>x</sub>/Pt) devices were fabricated and electrically analyzed. Both devices show reproducible and symmetrical threshold switching after an initial forming step. However, the kind of threshold switching was basically different. For the undoped VO<sub>x</sub>, threshold switching was identified as a low T<sub>C</sub>, VO<sub>2</sub>-type IMT, consistent with disappearance of the switching around 60 °C, whereas Cr-doped VO<sub>x</sub> switches up to > 90 °C, with a lower OFF-state current. These properties together with the poor conduction in the initial amorphous films make this new Cr-doped amorphous VO<sub>x</sub> material of high interest for selector material in both 2D 1S1R and a newly proposed 3D selector scheme.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"6 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114134107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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