H. Lung, Christopher P. Miller, Chia-Jung Chen, S. Lewis, J. Morrish, T. Perri, R. Jordan, H. Ho, T. Chen, W. Chien, Mark Drapa, T. Maffitt, J. Heath, Yutaka Nakamura, J. Okazawa, K. Hosokawa, M. BrightSky, R. Bruce, Huai-Yu Cheng, A. Ray, Y. Ho, C. Yeh, Wanki Kim, Sangbum Kim, Yu Zhu, C. Lam
{"title":"一种具有533MB/s读写速率和37.5ns访问延迟的双数据速率2 (DDR2)接口相变存储器","authors":"H. Lung, Christopher P. Miller, Chia-Jung Chen, S. Lewis, J. Morrish, T. Perri, R. Jordan, H. Ho, T. Chen, W. Chien, Mark Drapa, T. Maffitt, J. Heath, Yutaka Nakamura, J. Okazawa, K. Hosokawa, M. BrightSky, R. Bruce, Huai-Yu Cheng, A. Ray, Y. Ho, C. Yeh, Wanki Kim, Sangbum Kim, Yu Zhu, C. Lam","doi":"10.1109/IMW.2016.7493563","DOIUrl":null,"url":null,"abstract":"For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications\",\"authors\":\"H. Lung, Christopher P. Miller, Chia-Jung Chen, S. Lewis, J. Morrish, T. Perri, R. Jordan, H. Ho, T. Chen, W. Chien, Mark Drapa, T. Maffitt, J. Heath, Yutaka Nakamura, J. Okazawa, K. Hosokawa, M. BrightSky, R. Bruce, Huai-Yu Cheng, A. Ray, Y. Ho, C. Yeh, Wanki Kim, Sangbum Kim, Yu Zhu, C. Lam\",\"doi\":\"10.1109/IMW.2016.7493563\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.\",\"PeriodicalId\":365759,\"journal\":{\"name\":\"2016 IEEE 8th International Memory Workshop (IMW)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 8th International Memory Workshop (IMW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW.2016.7493563\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 8th International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2016.7493563","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications
For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.
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