2016 IEEE 8th International Memory Workshop (IMW)最新文献

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Improvement of Poly-Si Channel Vertical Charge Trapping NAND Devices Characteristics by High Pressure D2/H2 Annealing. 利用高压D2/H2退火改善多晶硅通道垂直电荷捕获NAND器件特性。
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495277
L. Breuil, J. Lisoni, R. Delhougne, C. L. Tan, J. van Houdt, G. Van den bosch, A. Furnémont
{"title":"Improvement of Poly-Si Channel Vertical Charge Trapping NAND Devices Characteristics by High Pressure D2/H2 Annealing.","authors":"L. Breuil, J. Lisoni, R. Delhougne, C. L. Tan, J. van Houdt, G. Van den bosch, A. Furnémont","doi":"10.1109/IMW.2016.7495277","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495277","url":null,"abstract":"In this paper, we investigate the effect of High Pressure Hydrogen or Deuterium Annealing on a vertical charge trapping NAND memory device. Strong improvement is obtained in Vt, subthreshold slope and drive current of the transistors by a better passivation of charge by either species in the bulk ONO memory stack, at the interface between ONO and Poly-Si channel, and in the bulk Poly-Si. Program / Erase and Retention remain identical, and no benefits could be observed by using D2 instead of H2 as passivating species in terms of robustness towards program/erase cycling damages.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126591941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers 用于汽车微控制器的高密度2.5V自对准分栅NVM单元嵌入40nm CMOS逻辑工艺的功能演示
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495271
L. Luo, Z. Teo, Y. Kong, F. Deng, J. F. Liu, F. Zhang, X. Cai, K. Tan, K. Lim, P. Khoo, S. Jung, S. Siah, D. Shum, C. M. Wang, J. Xing, G. Liu, Y. Diao, G. M. Lin, L. Tee, S. Lemke, P. Ghazavi, X. Liu, N. Do, K. Pey, K. Shubhakar
{"title":"Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers","authors":"L. Luo, Z. Teo, Y. Kong, F. Deng, J. F. Liu, F. Zhang, X. Cai, K. Tan, K. Lim, P. Khoo, S. Jung, S. Siah, D. Shum, C. M. Wang, J. Xing, G. Liu, Y. Diao, G. M. Lin, L. Tee, S. Lemke, P. Ghazavi, X. Liu, N. Do, K. Pey, K. Shubhakar","doi":"10.1109/IMW.2016.7495271","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495271","url":null,"abstract":"This paper for the first time successfully demonstrates a Logic-compatible, highly reliable, automotive-grade 16Mb flash macro with self- aligned, split-gate FG-based flash cell embedded into a 40nm Low Power CMOS with copper low-K interconnects. Key Features of the flash macro: Dual power supply with operation temperature from -40 to 150oC; Random Read access 10ns @ worst case condition; Low active and standby power; High raw endurance and data retention lifetime before using ECC. This technology provides large read current window which is compatible with both automotive MCU markets and low power mode tailored for smart card/industrial applications. The 16Mb Design test chip (DTC) with industry-leading cell size has demonstrated functionality with tight cell Vt and read current distributions. The SG NVM cell and erase gate are processed with self-alignment to gate spacer and polysilicon CMP (Chemical Mechanical Polishing) that can be easily integrated in a modular way to the standard logic process.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126744002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
SuperFlash® Scaling Aspects: Program Disturb SuperFlash®缩放方面:程序干扰
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495290
V. Markov, JinHo Kim, A. Kotov
{"title":"SuperFlash® Scaling Aspects: Program Disturb","authors":"V. Markov, JinHo Kim, A. Kotov","doi":"10.1109/IMW.2016.7495290","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495290","url":null,"abstract":"A systematic study of dominant program-disturb mechanisms in advanced embedded split-gate SuperFlash memory across ambient temperature ranging from -45°C to 175°C is presented. At low temperatures program disturb is initiated by trap-assisted band-to-band tunneling in the split-gate channel area and/or trap-assisted tunneling via thin select gate oxide and at high temperatures - by surface generation in select-gate channel. Effects of single traps on program disturb in split-gate memory have been analyzed. Good quality of thin select gate oxide and its interface with channel is important to meet stringent requirements of the wide-temperature embedded memory applications.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125865289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of Read Disturb on Incomplete Blocks in MLC NAND Flash Arrays MLC NAND闪存阵列中读干扰对不完整块的影响
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-01 DOI: 10.1109/IMW.2016.7495267
N. Papandreou, Thomas Parnell, T. Mittelholzer, H. Pozidis, T. Griffin, G. Tressler, T. Fisher, C. Camp
{"title":"Effect of Read Disturb on Incomplete Blocks in MLC NAND Flash Arrays","authors":"N. Papandreou, Thomas Parnell, T. Mittelholzer, H. Pozidis, T. Griffin, G. Tressler, T. Fisher, C. Camp","doi":"10.1109/IMW.2016.7495267","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495267","url":null,"abstract":"The effect of read disturb on partially programmed blocks of MLC NAND is evaluated using experimental data from 2y-, 1y- and 1x-nm Flash memory devices. We demonstrate that when a partially programmed block is exposed to a large number of reads before it is finalized in terms of page programming, the remaining pages will exhibit a significant bit error-rate (BER) increase. The page-BER is characterized in terms of program-erase cycles and read cycles and is further analyzed based on the programmed threshold voltage distributions. The impact of the page programming algorithm is also discussed.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128912651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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