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2016 IEEE 8th International Memory Workshop (IMW)最新文献

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A Si-Doped High-Performance WOx Resistance Memory Using a Novel Field-Enhanced Structure 一种新型场增强结构的掺硅高性能WOx电阻存储器
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7493564
K. Chiang, E. Lai, Chao-Hung Wang, Yu-Hsuan Lin, P. Tseng, Jau-Yi Wu, Ming-Hsiu Lee, Dai-Ying Lee, Yu-Yu Lin, F. Lee, K. Hsieh, Chih-Yuan Lu
{"title":"A Si-Doped High-Performance WOx Resistance Memory Using a Novel Field-Enhanced Structure","authors":"K. Chiang, E. Lai, Chao-Hung Wang, Yu-Hsuan Lin, P. Tseng, Jau-Yi Wu, Ming-Hsiu Lee, Dai-Ying Lee, Yu-Yu Lin, F. Lee, K. Hsieh, Chih-Yuan Lu","doi":"10.1109/IMW.2016.7493564","DOIUrl":"https://doi.org/10.1109/IMW.2016.7493564","url":null,"abstract":"We developed a simple structure that can enhance the local electric field thus reduce the forming and SET/RESET operation voltage for WOx ReRAM. Si-doped W film is used to further increase the initial resistance and improve the reliability properties. TCAD simulation shows that the field enhanced structure provides an equivalent electrical field that would only be achieved by very small conventional W plug ~ 10nm in size. Thus our novel but simple structure can provide the benefit of deep scaled device without expensive advanced lithography, and with better performance and reliability of larger devices. Furthermore,Si-doping provides an additional knob that allows resistance tuning to optimize the cell and array performance. The 1T1R memory array is well controlled and MLC operation can be reliably achieved by constant current RESET with logic states determined by cumulative RESET pulse duration.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116284358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Device Characteristics of Single-Gate Vertical Channel (SGVC) 3D NAND Flash Architecture 单栅极垂直通道(SGVC) 3D NAND闪存结构的器件特性
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495265
C. Wu, H. Lue, T. Hsu, C. Hsieh, Wei-Chen Chen, P. Du, C. Chiu, Chih-Yuan Lu
{"title":"Device Characteristics of Single-Gate Vertical Channel (SGVC) 3D NAND Flash Architecture","authors":"C. Wu, H. Lue, T. Hsu, C. Hsieh, Wei-Chen Chen, P. Du, C. Chiu, Chih-Yuan Lu","doi":"10.1109/IMW.2016.7495265","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495265","url":null,"abstract":"Device characteristics of single-gate vertical channel (SGVC) 3D NAND architecture are discussed in detail. The most important feature of SGVC is that the memory cell is a flat-channel device in 3D, different from the more often used gate-all-around (GAA) macaroni cell. Through various device optimizations, we have successfully produced excellent cell initial performances and more than 10V peak P/E window for each memory cell. In sharp contrast to the GAA cell, the SGVC flat cell naturally has superior layer-to-layer device uniformity that tolerates non-ideal vertical etching. Memory window managements in MLC and TLC applications are discussed. It is found that the major interference factor comes from the WL to WL interference. The root cause of WL interference is identified to be the channel potential interaction between the selected gate and neighbor WL in a junction-free 3D NAND. Random grain boundary trap effect further deteriorates the WL interference. It is found that the commonly adopted WL iterating algorithms in conventional FG NAND is also suitable for our SGVC 3D NAND to provide very tight Vt distribution for MLC and TLC applications.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124911118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Memory System Architecture Optimization for Enterprise All-RRAM Solid State Drives 面向企业级全rram固态硬盘的存储系统架构优化
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495283
Lorenzo Zuolo, C. Zambelli, A. Grossi, R. Micheloni, Stephen Bates, P. Olivo
{"title":"Memory System Architecture Optimization for Enterprise All-RRAM Solid State Drives","authors":"Lorenzo Zuolo, C. Zambelli, A. Grossi, R. Micheloni, Stephen Bates, P. Olivo","doi":"10.1109/IMW.2016.7495283","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495283","url":null,"abstract":"The Resistive RAM (RRAM) technology is emerging as one of the possible candidates in replacing state-of-the-art NAND Flash for Solid State Drives (SSDs) applications. However, the RRAM architectures developed so far evidence a granularity mismatch between their page size and the typical host application payloads, forcing the use of multi-plane approaches to mimic NAND Flash thus affecting the figures of merit (i.e., bandwidth, latency, and Quality of Service) of a potential \"all-RRAM\" SSD. In this work we present a RRAM memory system optimization acting both on the internal page size architecture and on the SSD's firmware to find the best configurations able to guarantee the highest performance metrics in enterprise-class SSD applications.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117070204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Storage As Fast As Rest of the System 存储与系统其他部分一样快
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495289
A. Foong, F. Hady
{"title":"Storage As Fast As Rest of the System","authors":"A. Foong, F. Hady","doi":"10.1109/IMW.2016.7495289","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495289","url":null,"abstract":"Ultra-low latency, high endurance SSDs are poised to enter the market, based on 3D XPoint™ memory. Here we show that for these new SSDs and modern platforms, storage latency is equally divided between the SSD and the rest-of platform. We summarize some of the recent system level optimizations that make this possible. Such low latency storage offers a potential for applications to use storage as a resource in place of memory. We describe a few examples of use case analyses that we have undertaken. Finally we comment on use of 3D XPoint memory accessed as system memory rather than storage.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126746035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
High Temperature Data Retention of Ferroelectric Memory on 130nm and 180nm CMOS 铁电存储器在130nm和180nm CMOS上的高温数据保留
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495274
J. Rodriguez, C. Zhou, T. Graf, R. Bailey, Michael Wiegand, T. Wang, M. Ball, H. Wen, K. Udayakumar, S. Summerfelt, T. San, T. Moise
{"title":"High Temperature Data Retention of Ferroelectric Memory on 130nm and 180nm CMOS","authors":"J. Rodriguez, C. Zhou, T. Graf, R. Bailey, Michael Wiegand, T. Wang, M. Ball, H. Wen, K. Udayakumar, S. Summerfelt, T. San, T. Moise","doi":"10.1109/IMW.2016.7495274","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495274","url":null,"abstract":"Systematic evaluation of ferroelectric memory (FRAM) data retention mechanisms under high temperature exposure are reported. The FRAM devices are embedded on ultra-low power, analog-enhanced 130nm and 180nm CMOS technologies. Capability of the FRAM to retain data through 260°C Pb-free solder assembly reflow is demonstrated. The 130nm FRAM is shown to achieve the equivalent of 10 years data retention at 125°C, with intrinsic margin comparable to the 180nm FRAM, previously shown to achieve 10 years at 125°C retention.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130182882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Demonstration of Reliable Triple-Level-Cell (TLC) Phase-Change Memory 可靠的三电平单元(TLC)相变存储器的演示
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495263
M. Stanisavljevic, H. Pozidis, A. Athmanathan, N. Papandreou, T. Mittelholzer, E. Eleftheriou
{"title":"Demonstration of Reliable Triple-Level-Cell (TLC) Phase-Change Memory","authors":"M. Stanisavljevic, H. Pozidis, A. Athmanathan, N. Papandreou, T. Mittelholzer, E. Eleftheriou","doi":"10.1109/IMW.2016.7495263","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495263","url":null,"abstract":"Although phase-change memory is admittedly the most mature of the emerging nonvolatile memory technologies, its eventual mass production and market adoption may depend on its cost, in particular in comparison to DRAM and to NAND Flash. In addition to process complexity, another major factor that affects the cost of a memory technology is the capability to store multiple bits per memory cell. As a notable example, Triple-Level-Cell (TLC) NAND Flash is currently leading the Flash capacity shipments. With this as motivation, we present a combination of electrical sensing techniques and signal processing technologies to demonstrate, for the first time, the viability of reliable, nonvolatile, TLC storage in phase-change memory cells after extended endurance cycling and temperature stress.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124348843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Junctionless Array with Ultrathin PolyTiN Floating Gate and HfAlO Based Intergate Dielectric for Sub-15nm Planar NAND Flash 亚15nm平面NAND闪存用超薄聚锡浮栅和基于HfAlO的集成栅介电无结阵列
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495282
P. Blomme, J. Versluis, M. Ercken, Laurent Sourieau, H. Hody, G. Vecchio, V. Paraschiv, C. L. Tan, G. Van den bosch, J. van Houdt
{"title":"Junctionless Array with Ultrathin PolyTiN Floating Gate and HfAlO Based Intergate Dielectric for Sub-15nm Planar NAND Flash","authors":"P. Blomme, J. Versluis, M. Ercken, Laurent Sourieau, H. Hody, G. Vecchio, V. Paraschiv, C. L. Tan, G. Van den bosch, J. van Houdt","doi":"10.1109/IMW.2016.7495282","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495282","url":null,"abstract":"We look at the challenges for scaling planar NAND flash for sub-15nm nodes, and show the implementation of hybrid polymetal floating gate (FG), HfAlO based IGD, junctionless array, WL trimming, and EUV spacer defined double patterning in a fully planar NAND Flash array with good programming performance.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134173592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NAND Flash Memory Revolution NAND闪存革命
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495285
S. Aritome
{"title":"NAND Flash Memory Revolution","authors":"S. Aritome","doi":"10.1109/IMW.2016.7495285","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495285","url":null,"abstract":"NAND Flash memory became a standard semiconductor nonvolatile memory. Everyone in the world has widely used NAND Flash memory in many applications, such as digital camera, USB drive, portable music player, smartphone, and tablet-PC. The cloud data server started to use SSD (Solid State Drive) which was based on NAND Flash memory. Recently, 3-dimensional (3D) NAND flash memory was developed and started mass-production for reducing bit cost. By using 3D NAND flash memory, an advanced SSD has been intensively developed for high performance, and low power consumption, namely ecological environment. In this paper, NAND Flash memory technologies are discussed in the past, present and future.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"359 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132608322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Ultra Low Power Charge Pump with Multi-Step Charging and Charge Sharing 超低功率充电泵与多步充电和充电共享
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495294
Steve Ngueya W, Julien Mellier, Stephane Ricard, J. Portal, H. Aziza
{"title":"Ultra Low Power Charge Pump with Multi-Step Charging and Charge Sharing","authors":"Steve Ngueya W, Julien Mellier, Stephane Ricard, J. Portal, H. Aziza","doi":"10.1109/IMW.2016.7495294","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495294","url":null,"abstract":"A new approach for improving the power efficiency of the conventional four-phase charge pump is presented. Based on the multi-step capacitor charging and the charge sharing concept, the charge pump design is able to reduce the overall power consumption by 35% compared to the conventional four-phase charge pump and by 15% compared to a charge sharing charge pump, for an output current of 200μA with 12V output voltage.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115788685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Doped Gd-O Based RRAM for Embedded Application 基于掺杂Gd-O的嵌入式RRAM
2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI: 10.1109/IMW.2016.7495266
C. Y. Chen, L. Goux, A. Fantini, A. Redolfi, G. Groeseneken, M. Jurczak
{"title":"Doped Gd-O Based RRAM for Embedded Application","authors":"C. Y. Chen, L. Goux, A. Fantini, A. Redolfi, G. Groeseneken, M. Jurczak","doi":"10.1109/IMW.2016.7495266","DOIUrl":"https://doi.org/10.1109/IMW.2016.7495266","url":null,"abstract":"In this paper we propose a novel oxide-based RRAM stack using hygroscopic oxide, doped Gd-O, as resistive switching layer integrated in a CMOS friendly flow. Operating at 50μA, the stack features large resistive window (>x100) and superior endurance lifetime (10^12) which is to our knowledge the record lifetime for CMOS compatible RRAM devices. Detailed benchmarking between conventional oxide-based RRAM is also made throughout this study.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132034399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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