亚15nm平面NAND闪存用超薄聚锡浮栅和基于HfAlO的集成栅介电无结阵列

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI:10.1109/IMW.2016.7495282

P. Blomme, J. Versluis, M. Ercken, Laurent Sourieau, H. Hody, G. Vecchio, V. Paraschiv, C. L. Tan, G. Van den bosch, J. van Houdt

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引用次数: 0

摘要

我们研究了在sub-15nm节点上扩展平面NAND闪存的挑战，并展示了在具有良好编程性能的全平面NAND闪存阵列中实现混合多金属浮栅(FG)、基于HfAlO的IGD、无结阵列、WL修整和EUV间隔器定义的双图案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Junctionless Array with Ultrathin Poly\TiN Floating Gate and HfAlO Based Intergate Dielectric for Sub-15nm Planar NAND Flash

We look at the challenges for scaling planar NAND flash for sub-15nm nodes, and show the implementation of hybrid poly\metal floating gate (FG), HfAlO based IGD, junctionless array, WL trimming, and EUV spacer defined double patterning in a fully planar NAND Flash array with good programming performance.

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2016 IEEE 8th International Memory Workshop (IMW)

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