Yong Kyu Lee, Hongkook Min, Changmin Jeon, B. Seo, Gayoung Lee, Eunkang Park, Donghyun Kim, Changhyun Park, B. Kwon, Minsu Kim, Bongsang Lee, Duckhyung Lee, Hyosang Lee, Jisung Kim, Sunghee Cho
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引用次数: 2
Abstract
We present a highly scalable 2nd generation 45-nm split-gate embedded flash, which has been scaled of 40% unit-cell-size (almost same size with 28-nm technology node) from the 1st generation 45-nm embedded flash without using extra masks, processes and advanced-equipment. By optimizing process of triple-gate flash architecture and implementing several design methodologies, high speed operation (10ns random access time, 25us write time and less than 2ms erase operation) and robust reliability (1M cycle, 20 retention) are achieved. It has been successfully verified in range of 1Mb up to 16Mb density flash IPs.
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