利用2mbit 1T-1MTJ STT-MRAM测试芯片演示On-Via MTJ成品率的提高

2016 IEEE 8th International Memory Workshop (IMW) Pub Date : 2016-05-15 DOI:10.1109/IMW.2016.7495264

H. Koike, S. Miura, H. Honjo, Toshinari Watanabe, Hideo Sato, S. Sato, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, M. Muraguchi, M. Niwa, Kenchi Ito, S. Ikeda, H. Ohno, T. Endoh

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引用次数: 7

摘要

为了实现与现有动态随机存储器(DRAM)相媲美的高密度自旋-传递-转矩磁随机存储器(STT-MRAM)器件，开发缩小存储单元尺寸的新技术是关键。我们已经报道了一种基于化学-机械抛光(CMP)的磁隧道结(MTJs)制备技术，该技术可以大大减少通孔上方的存储单元面积。本文首先将MTJ制备技术引入到兆比特级STT-MRAM测试芯片中，并演示了该技术对存储单元运算成品率的提高。

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Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip

To realize a high-density spin-transfer-torque magnetic random access memory (STT-MRAM) device comparable with a current dynamic random access memory (DRAM) device, it is a key to develop a new technology for memory cell size reduction. We have already reported a chemical- mechanical-polishing(CMP)-based preparation technology for magnetic tunnel junctions (MTJs) above the via holes that can drastically reduce memory cell area. In this paper, we first introduce the MTJ preparation technology to the mega-bit class STT-MRAM test chip, and demonstrate the improvement of memory-cell operation yield.

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2016 IEEE 8th International Memory Workshop (IMW)

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