J. Kluge, G. Navarro, V. Sousa, N. Castellani, S. Blonkowski, R. Annunziata, P. Zuliani, L. Perniola
{"title":"High Operating Temperature Reliability of Optimized Ge-Rich GST Wall PCM Devices","authors":"J. Kluge, G. Navarro, V. Sousa, N. Castellani, S. Blonkowski, R. Annunziata, P. Zuliani, L. Perniola","doi":"10.1109/IMW.2016.7495273","DOIUrl":null,"url":null,"abstract":"The reliability of optimized Ge-rich GST \"Wall\" Phase Change Memory (PCM) devices is investigated at high operating temperatures. Endurance of more than 107 cycles is ensured up to 175 °C. A cell thermal resistance 45% higher wrt standard GST devices is demonstrated, granting reduced cell to cell thermal crosstalk. Increased temperatures show to have a limited impact on the programming speed. Finally, specific programming sequences are proposed to reduce the drift of intermediate resistance states at high temperature.","PeriodicalId":365759,"journal":{"name":"2016 IEEE 8th International Memory Workshop (IMW)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 8th International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2016.7495273","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The reliability of optimized Ge-rich GST "Wall" Phase Change Memory (PCM) devices is investigated at high operating temperatures. Endurance of more than 107 cycles is ensured up to 175 °C. A cell thermal resistance 45% higher wrt standard GST devices is demonstrated, granting reduced cell to cell thermal crosstalk. Increased temperatures show to have a limited impact on the programming speed. Finally, specific programming sequences are proposed to reduce the drift of intermediate resistance states at high temperature.