2011 IEEE International SOC Conference最新文献

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Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems 热感知三维片上网络系统非平稳不规则网格的传输层辅助路由
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085086
Chih-Hao Chao, Tsu-Chu Yin, Shu-Yen Lin, A. Wu
{"title":"Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems","authors":"Chih-Hao Chao, Tsu-Chu Yin, Shu-Yen Lin, A. Wu","doi":"10.1109/SOCC.2011.6085086","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085086","url":null,"abstract":"Thermal issue is important for 3D Network-on-Chip systems. To ensure thermal safety, run-time thermal management is required. However, the regulation of temperature requires throttling of the near-overheated router, which makes the topology become Non-Stationary Irregular mesh (NSI-mesh). To successfully deliver packet in NSI-mesh, we propose the Transport Layer Assisted Routing (TLAR) scheme and two algorithms for thermal-aware 3D NoC. Based on the experimental results, the proposed routing scheme can reduce the latency over 57.5% and improve the throughput above 1.47x.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126826750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
PVT variations aware optimal sleep vector determination of dual VT domino OR circuits PVT变化意识到双VT多米诺或电路的最佳睡眠向量确定
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085092
Na Gong, Jinhui Wang, R. Sridhar
{"title":"PVT variations aware optimal sleep vector determination of dual VT domino OR circuits","authors":"Na Gong, Jinhui Wang, R. Sridhar","doi":"10.1109/SOCC.2011.6085092","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085092","url":null,"abstract":"In this paper, determining optimal leakage vector for dual Vt domino OR circuits is explored under process, supply voltage, and temperature (PVT) variations based on 65 nm bulk and 45 nm high k/metal gate (HK+MG) technologies, while considering design parameters, environmental parameters, working characteristics of circuits, and application cases. It concludes that the high clock signal with high inputs (CHIH) vector is the optimal sleep vector for practical low leakage register files applications, and the HK+MG technology further highlights the effectiveness of the CHIH vector as compared to other vectors.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116155751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A SAR ADC BIST for simplified linearity test 用于简化线性度测试的SAR ADC BIST
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085122
An-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting
{"title":"A SAR ADC BIST for simplified linearity test","authors":"An-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting","doi":"10.1109/SOCC.2011.6085122","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085122","url":null,"abstract":"A built-in self-test (BIST) scheme to quickly estimate differential nonlinearity (DNL) is proposed. The proposed scheme detects serious code deviation and reduces needed samples. Compared with the conventional code density test, the scheme reduces 97% sample count for a 10-bit approximation register analog-to-digital converters (SAR ADC).","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114692907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
TSV-based 3D-IC placement for timing optimization 基于tsv的3D-IC放置时间优化
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085087
Yi-Rong Chen, Hung-Ming Chen, Shih-Ying Liu
{"title":"TSV-based 3D-IC placement for timing optimization","authors":"Yi-Rong Chen, Hung-Ming Chen, Shih-Ying Liu","doi":"10.1109/SOCC.2011.6085087","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085087","url":null,"abstract":"The semiconductor technology continue its advnacement in 3D-IC circuit. The concept of 3D-IC introduces additional dimension in latest designs by using stack structures with through-silicon via (TSV). 3D ICs replace long interconnect in 2D ICs with TSV cells. However, optimization in terms of 3DIC is still immature in many aspects. There still exist problems in placement of standard cells and TSV cells in terms of timing optimization. In this paper, we proposed a methodology on cell placement by applying min-cut partitioning in one layer after layer assignment and address alignment constraint simultaneously. We applied Simulated Annealing to optimize timing and wirelength reduction. In final stage, a greedy legalization procedure is implemented to remove operlaps between cells and TSV cells. Experimental results show that both the wirelengths and the delay of critical paths in 3DICs are much superior compare to 2D ICs.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114749457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
“Post silicon debug of SOC designs” SOC设计的后晶片调试
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085147
Virendra Singh, M. Fujita
{"title":"“Post silicon debug of SOC designs”","authors":"Virendra Singh, M. Fujita","doi":"10.1109/SOCC.2011.6085147","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085147","url":null,"abstract":"Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125954235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A gate sizing method for glitch power reduction 一种减小毛刺功率的栅极尺寸方法
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085070
Lei Wang, M. Olbrich, E. Barke, Thomas Büchner, Markus Bühler, P. Panitz
{"title":"A gate sizing method for glitch power reduction","authors":"Lei Wang, M. Olbrich, E. Barke, Thomas Büchner, Markus Bühler, P. Panitz","doi":"10.1109/SOCC.2011.6085070","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085070","url":null,"abstract":"Due to the difficulty in estimating dynamic power at the gate level, a quantity called power metric and its efficient calculation method are introduced in this work. Based on the proposed power metric, a heuristic gate sizing algorithm for glitch power reduction is proposed for semi-custom design. The proposed heuristic algorithm minimizes the total power metric of a circuit. According to the experimental results on 8 ISCAS85 benchmark circuits and 5 real industrial circuits, more than 30% average glitch power reduction and 15.5% average total power reduction can be achieved by means of the proposed algorithm, respectively. The achieved improvements on power and area both are more than those by means of conventional gate sizing algorithms.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122634986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM 低电压SRAM和9T电源反馈SRAM的可扩展性
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085135
Janna Mezhibovsky, A. Teman, A. Fish
{"title":"Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM","authors":"Janna Mezhibovsky, A. Teman, A. Fish","doi":"10.1109/SOCC.2011.6085135","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085135","url":null,"abstract":"Recent research has shown that minimum energy operation of digital circuits is in the sub-threshold region, and a good trade-off between power and performance can be achieved through operation at near threshold supply voltages. However, due to process variations and device mismatch at nanoscale technology nodes, voltage scaling of standard SRAMs is limited to strong-inversion operation. One of the techniques for enabling operation at low voltages is implementation of a Supply Feedback mechanism that internally weakens the pull-up current during write operations. This concept was recently implemented in a 9T Supply Feedback SRAM (SF-SRAM) cell, fabricated and successfully tested in a 40nm CMOS technology. In this paper, we review existing low voltage SRAM solutions, overview the SF-SRAM cell, and show its scalability into deep nanoscale technologies by using the 22nm predictive model.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126295155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Configurable baseband designs and implementations of WiMAX/LTE dual systems based on multi-core DSP 基于多核DSP的WiMAX/LTE双系统的可配置基带设计与实现
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085146
Jen-Yuan Hsu, Chien-Yu Kao, P. Kuo, Pangan Ting
{"title":"Configurable baseband designs and implementations of WiMAX/LTE dual systems based on multi-core DSP","authors":"Jen-Yuan Hsu, Chien-Yu Kao, P. Kuo, Pangan Ting","doi":"10.1109/SOCC.2011.6085146","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085146","url":null,"abstract":"This paper deals with configurable baseband designs for IEEE 802.16m and TD-LTE systems. Thanks to the similar frame structures and signal flows between these two standards, the configurable designs and implementations of WiMAX/LTE dual system are feasible. By comparing the signal processing flows in both systems, a generic architecture, which can be configured as either a base station or a mobile station, is proposed. A realization using Texas Instruments (TI) multi-core DSP, Xilinx FPGA, ADC, DAC and RF transceivers is accomplished and a real-time video demo is delivered.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132829863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Yield-award placement optimization for Switched-Capacitor analog integrated circuits 开关电容模拟集成电路的产量奖励放置优化
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085127
Chien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, C. Wey
{"title":"Yield-award placement optimization for Switched-Capacitor analog integrated circuits","authors":"Chien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, C. Wey","doi":"10.1109/SOCC.2011.6085127","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085127","url":null,"abstract":"Paralleling square unit capacitors have been commonly used for Switched-Capacitor circuits to achieve higher accurate capacitor ratio. However, the capacitor ratio may be shifted due to the wire interconnection of these unit capacitors. The small capacitor ratio shift may cause a significant yield drop. The ratio shift can be reduced by using extra circuitry to achieve parasitic insensitive design. This study presents a simple a layout modification to alleviate the ratio shift, thus enhancing yield, without requiring extra circuitry.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133549738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Double-differential recording and AGC using amplifier ASIC 双差分记录和AGC使用放大器ASIC
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085121
Shin-Liang Deng, Chun-Yi Li, R. Rieger
{"title":"Double-differential recording and AGC using amplifier ASIC","authors":"Shin-Liang Deng, Chun-Yi Li, R. Rieger","doi":"10.1109/SOCC.2011.6085121","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085121","url":null,"abstract":"An automatic gain control circuit (AGC) and a circuit for double-differential (DD) recording are implemented using an integrated variable gain circuit. The integrated circuit enables gain trimming by variation of the chip clock timing. A microcontroller is used to provide the clocks. AGC and DD setups with a simple 2-chip and 3-chip system respectively are realized. Measured results confirm a gain tuning range of 22.7 dB and interference suppression of 41.4 dB in the balanced DD arrangement, and power consumption of 318 µW.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122252680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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