Matheus T. Moreira, B. Oliveira, Julian J. H. Pontes, Ney Laert Vilar Calazans
{"title":"A 65nm standard cell set and flow dedicated to automated asynchronous circuits design","authors":"Matheus T. Moreira, B. Oliveira, Julian J. H. Pontes, Ney Laert Vilar Calazans","doi":"10.1109/SOCC.2011.6085103","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085103","url":null,"abstract":"This work proposes a new design flow for rapid creation and characterization of standard cell sets for asynchronous design. The flow is fully automated except for the cell layout generation step. It has been applied to the design of a standard cell set supporting the Teak asynchronous synthesis tool. Cells use a 65 nm gate length commercial CMOS process. An asynchronous RSA cryptography circuit provides the design flow validation.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115496391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VFSMC - a core for cycle accurate multithreaded processing in hard real-time Systems-on-Chip","authors":"S. Brandstätter, M. Huemer","doi":"10.1109/SOCC.2011.6085111","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085111","url":null,"abstract":"This paper focuses on the design, implementation and benchmarking of a core for cycle accurate multithreaded processing in hard real-time systems-on-chip. The reason to force this development is the increasing number of system-on-chip applications which require hard real-time or even cycle accurate execution of parallel tasks. Benchmarks show that the core presented in this work overcomes these barriers by implementing a well defined instruction set and an execution pipeline which allows fine-grain temporal multithreading.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115583019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chang-Hsin Cheng, Chun-Lung Hsu, Chung-Kai Liu, Shih-Yin Lin
{"title":"High reliability built-in self-detection and self-correction design for DCT/IDCT application","authors":"Chang-Hsin Cheng, Chun-Lung Hsu, Chung-Kai Liu, Shih-Yin Lin","doi":"10.1109/SOCC.2011.6085106","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085106","url":null,"abstract":"This paper proposes an efficient built-in self-detection and self-correction techniques to detect and correct error in discrete cosine transform (DCT)/inverse discrete cosine transform (IDCT) based on the biresidue codes. On the other hand, any single bit error of DCT/IDCT can be efficiently detected or corrected. Experimental results show the proposed BISDC architecture has good performance in throughput with reasonable area overhead and high reliability.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127917130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tzu-Chun Shih, Tsan-Wen Chen, W. Sung, Ping-Yuan Tsai, Chen-Yi Lee
{"title":"An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications","authors":"Tzu-Chun Shih, Tsan-Wen Chen, W. Sung, Ping-Yuan Tsai, Chen-Yi Lee","doi":"10.1109/SOCC.2011.6085118","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085118","url":null,"abstract":"This work proposes an orthogonal frequency division multiplexing (OFDM) based baseband transceiver design for wireless body area network (WBAN) application. Based on the analysis of the WBAN operation behavior, high transmission data rate and low power implementation techniques are proposed to reduce the transmission energy. An electrocardiography (ECG) transmission platform is also established with proposed design for system evaluation. This chip is implemented in a 90nm CMOS technology with the core size of 2.85 mm2, and this baseband transceiver dissipates 357.14 uW with supply voltage 0.5 V. The proposed chip provides maximum 9.7 Mbps data rate, resulting in active duty cycle of 0.1763% and the transmission energy of 0.37 nJ / bit.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130411084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Feasibility study for communication over Power Distribution Networks of microprocessors","authors":"R. Thirugnanam, D. Ha","doi":"10.1109/SOCC.2011.6085131","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085131","url":null,"abstract":"In this paper, we explore use of the Power Distribution Network (PDN) of a microprocessor as a communication channel for testing, debug, and diagnosis purposes. Feasibility of the proposed communication method is studied through direct measurements of microprocessor PDNs. Decoupling capacitors attached to the package make the PDN a low pass filter. However, the parasitic inductance of a decoupling capacitor becomes more significant beyond the self-resonant frequency, and our measurements on Intel microprocessor PDNs indicate that pass bands exist at frequencies beyond several 100 MHz. Impulse ultra wideband signals are a good candidate for communications over PDNs.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132943175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Hsieh, J. Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen
{"title":"System power analysis with DVFS on ESL virtual platform","authors":"W. Hsieh, J. Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen","doi":"10.1109/SOCC.2011.6085102","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085102","url":null,"abstract":"In this work, we propose an electronic system-level (ESL) power estimation framework which can support several low power methodologies such as dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM). Based on the proposed framework, designers can analyze the system power and develop the suitable low power strategies for different applications in the early design stage. The proposed framework had been applied to a heterogeneous multi-core platform. We rapidly characterized the required power models by using physical power measurement to construct the ESL power estimation environment. According to the experimental results, using the proposed framework can have quite accurate power estimation and correct power trend prediction in different voltage/frequency conditions. We also had demonstrated that the low power methodologies can be analyzed and simulated based on this framework.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122759553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A CAD methodology for automatic topology selection & sizing","authors":"S. Maji, P. Mandal","doi":"10.1109/SOCC.2011.6085101","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085101","url":null,"abstract":"Over the years, as system on chip is increasingly incorporating analog functionalities, there is a need of a tool, which can automate the analog topology selection and sizing flow. We develop one efficient methodology to automatically select the best topology given only the user specifications. The proposed topology selection is a multilevel screening process inherited from geometric programming (GP) by sequentially introducing sub-sets of requirements. This helps to prune out unfit topologies at early stage and hence not costing much computational effort. Use of GP ensures fast convergence with optimal solution. Apart from the speed advantage, compared to the existing literature, methodology has better representation of topology performance expressions. We propose to use two levels of performance expressions. First one is technology independent and the second one is technology specific. This bifurcation of performance expressions help in quick technology migration. Third contribution is automatic node expression generation which are required for dc performance evaluation. The proposed methodology is used for selecting optimal error amplifier topology for low dropout regulator (LDO).","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124971679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rajaram Mohan Roy Koppula, S. Balagopal, V. Saxena
{"title":"Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs","authors":"Rajaram Mohan Roy Koppula, S. Balagopal, V. Saxena","doi":"10.1109/SOCC.2011.6085120","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085120","url":null,"abstract":"A design methodology for synthesizing power-optimized decimation filters for wideband Delta Sigma (ΔΣ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuous-time ΔΣ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45nm CMOS technology occupies a layout area of 0.12mm2 and consumes 8 mW power from the 1.1V supply.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128838128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power characteristics of Asynchronous Networks-on-Chip","authors":"Maher Rashed, Mohamed A. Abd El-Ghany, M. Ismail","doi":"10.1109/SOCC.2011.6085125","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085125","url":null,"abstract":"Power characteristics of different Asynchronous Network on Chip (NoC) architectures are developed. Among different NoC architectures, the Butterfly Fat Tree (BFT) dissipates the minimum power. With increasing the number of IP blocks, the relative power consumption of the interconnects and the associate repeaters of the Asynchronous NoC architecture decreases as compared to the power consumption of the network switches. The power dissipation of the Asynchronous architecture is decreased by up to 57% as compared to the power dissipation of the conventional Synchronous architecture. The BFT is more efficient with increasing the number of IP blocks.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133236849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Configurable workload generators for multicore architectures","authors":"Amayika Panda, A. Avakian, R. Vemuri","doi":"10.1109/SOCC.2011.6085077","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085077","url":null,"abstract":"Proposed multicore architectures are usually evaluated using two types of benchmarks: application and synthetic. Application benchmarks use well understood computations to generate well defined workloads. In contrast, synthetic benchmarks are tunable to generate a range of custom workloads. Both classes are currently limited. Existing application benchmarks are inflexible. And the options offered by synthetic benchmarks are too limited to generate a large variety of workload patterns. In this paper we propose novel workload generation methodologies that allow system developers to generate custom benchmarks for desired workload conditions for a variety of existing and multicore architectures. Specifically we describe two configurable workload generators, which we name ConWork and CompWork. ConWork is a configurable synthetic workload generator using which artificial traffic among the processors and memories can be generated. CompWork is a configurable computational workload generator, which can be used to specify vector and matrix applications so as to elicit the desired computational workloads among the processors. Together the two generators provide a number of options to generate workloads to evaluate a variety of performance metrics of existing and emerging multicore architectures including bus based SoCs, packet switching NoCs and hybrids.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}