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2011 IEEE International SOC Conference最新文献

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A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode 具有IAS-DSP和超低功耗计量模式的单相电能计量SoC
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085091
Yan Zhao, N. Tan, Kun-Ming Yang, Shupeng Zhong, Changyou Men
{"title":"A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode","authors":"Yan Zhao, N. Tan, Kun-Ming Yang, Shupeng Zhong, Changyou Men","doi":"10.1109/SOCC.2011.6085091","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085091","url":null,"abstract":"A single-phase energy metering SoC in TSMC 0.25um mixed-mode embedded FLASH technology is designed. While integrating four channel sigma-delta ADCs, PLL, oscillation circuit, regulators, temperature sensor, 8-bit CPU core, 32K byte FLASH memory, 1K byte SRAM memory, energy metering engine, and various on-chip peripherals, a small die size is achieved due to the implement of an 32-bit fixed-point Instruction and Architecture Specific DSP (IAS-DSP) to conduct the carefully designed multi-rate energy metering algorithm. To satisfy critical power restrictive applications, several ultra low power metering modes are designed. With these modes and the IAS-DSP, there is only about 100uA current dissipation while metering accuracy still meets industrial standards. The experimental results also prove excellent EMI rejection features. The chip is currently in production and millions has been shipped.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132974293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of complex circuits using the Via-Configurable transistor array regular layout fabric 采用通孔可配置晶体管阵列规则布局结构设计复杂电路
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085126
M. Pons, F. Moll, A. Rubio, J. Abella, X. Vera, Antonio González
{"title":"Design of complex circuits using the Via-Configurable transistor array regular layout fabric","authors":"M. Pons, F. Moll, A. Rubio, J. Abella, X. Vera, Antonio González","doi":"10.1109/SOCC.2011.6085126","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085126","url":null,"abstract":"Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High performance multi-engine regular expression processing 高性能多引擎正则表达式处理
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085117
T. Arumugam, S. Sezer, D. Burns, V. Vasu
{"title":"High performance multi-engine regular expression processing","authors":"T. Arumugam, S. Sezer, D. Burns, V. Vasu","doi":"10.1109/SOCC.2011.6085117","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085117","url":null,"abstract":"This paper discusses a novel multi-engine hardware based regular expression processor. Regular expression is widely used as a pattern matching technique to detect presence of malicious content in Internet traffic. In the proposed approach, parallel IP flows are handled by separate regular expression processing engines, sharing a common program memory. The proposed architecture has been designed and implemented for a four engine system using Altera Stratix IV technology. With four independent engines operating at 185.43 MHz the achievable system bandwidth is estimated to be 5.93 Gbps, using approximately 20K ALUTs.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121748306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization 考虑能量最小化和产量最大化的亚阈值电路设计策略
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085076
J. Kawashima, H. Ochi, Hiroshi Tsutsui, Takashi Sato
{"title":"A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization","authors":"J. Kawashima, H. Ochi, Hiroshi Tsutsui, Takashi Sato","doi":"10.1109/SOCC.2011.6085076","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085076","url":null,"abstract":"This paper investigates a design strategy for sub-threshold circuits focusing on energy-consumption minimization and yield maximization under process variations. It is shown that 1) the minimum operation voltage (VDDmin) of a circuit is dominated by FFs, and it can be improved by appropriate transistor sizing, 2) VDDmin of a FF is stochastically modeled by a log-normal distribution, 3) VDDmin of a large circuit can be estimated using the above model without extensive Monte-Carlo simulations, and 4) improving VDDmin may substantially contribute to reduce energy consumption.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127934031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel adaptive keeper LBL technique for low power and high performance register files 一种低功耗高性能寄存器文件的自适应保存器LBL技术
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085071
Na Gong, Geng Tang, Jinhui Wang, R. Sridhar
{"title":"Novel adaptive keeper LBL technique for low power and high performance register files","authors":"Na Gong, Geng Tang, Jinhui Wang, R. Sridhar","doi":"10.1109/SOCC.2011.6085071","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085071","url":null,"abstract":"This paper develops a novel adaptive keeper local bit line (LBL) technique to achieve low power and high performance register files design. To avoid increasing the implementation hardware overhead, the proposed technique employs a clock-combined unit to generate the body voltage of keeper. We evaluate the effectiveness of the proposed technique in a two-cycle 64-entries×32b register file design for 8GHz operation in 1V, 32nm high-K Metal-Gate technology. HSPICE simulation results show that the delay time is reduced by 29% and the power consumption is reduced by 36.1%–46.2% depending on the number of reading ports, as compared to the tradition register files design. Moreover, the proposed technique shows good robustness to noise and process variations.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130041441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dynamic calibration of feedback DAC non-linearity for a 4th order CT sigma delta for digital hearing aids 数字助听器四阶CT σ δ反馈DAC非线性的动态校准
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085129
S. R. Naqvi, I. Deligoz, S. Kiaei, B. Bakkaloglu
{"title":"Dynamic calibration of feedback DAC non-linearity for a 4th order CT sigma delta for digital hearing aids","authors":"S. R. Naqvi, I. Deligoz, S. Kiaei, B. Bakkaloglu","doi":"10.1109/SOCC.2011.6085129","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085129","url":null,"abstract":"In this paper we present a calibration scheme for calibrating the 2<sup>nd</sup> order harmonic distortion of feedback DAC used in a 4<sup>th</sup> order CT-ΣΔ. This scheme was implemented in a 0.25um CMOS process with a supply voltage of 1.2V, the 4<sup>th</sup> order CT-ΣΔ was able to achieve 68dB measured SNR, while the 2<sup>nd</sup> order harmonic was reduced by about 20dB suppressing it to the thermal noise floor.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124446516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits 用于抑制地门控集成电路模式转换噪声的睡眠信号摆率调制
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085093
Hailong Jiao, V. Kursun
{"title":"Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits","authors":"Hailong Jiao, V. Kursun","doi":"10.1109/SOCC.2011.6085093","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085093","url":null,"abstract":"Ground bouncing noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in multi-threshold CMOS (MTCMOS) circuits. Single-phase and multi-phase sleep signal slew rate modulation techniques are explored in this paper to drastically suppress ground bouncing noise in MTCMOS circuits. Reactivation time, reactivation energy, leakage power consumption, and layout area of different MTCMOS circuits are characterized under an equi-noise constraint with a UMC 80nm CMOS technology.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117128529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip 基于FPGA的片上网络虚拟通道架构研究
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085089
Ye Lu, J. McCanny, S. Sezer
{"title":"Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip","authors":"Ye Lu, J. McCanny, S. Sezer","doi":"10.1109/SOCC.2011.6085089","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085089","url":null,"abstract":"A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115233230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Technology trends and implications on SoC design SoC设计的技术趋势和影响
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085094
J. Burns
{"title":"Technology trends and implications on SoC design","authors":"J. Burns","doi":"10.1109/SOCC.2011.6085094","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085094","url":null,"abstract":"Semiconductor technology evolution is increasingly driven by disruptive innovations rather than classical 2D scaling. These innovations, and potential new technologies such as 3D integration, will allow device counts to continue to increase well beyond the 1 – 2 billion of today's chips. With this ongoing growth in available devices the challenges in design quality and productivity will also grow, along with the investments needed for technology development and manufacturing. The challenges for chip and system designs lie in finding affordable means to harness these capabilities to deliver significant system level value to end users. In this presentation I will explore several of these technology trends, in the context of SoC design for high-performance systems, and describe several of the initiatives underway in IBM Research to address them.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131946311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An analytical model to estimate PCM failure probability due to process variations 一个分析模型来估计由于工艺变化导致的PCM失效概率
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085128
Mu-Tien Chang, B. Jacob
{"title":"An analytical model to estimate PCM failure probability due to process variations","authors":"Mu-Tien Chang, B. Jacob","doi":"10.1109/SOCC.2011.6085128","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085128","url":null,"abstract":"Phase change memory (PCM) features nonvolatility, high density, and superior power efficiency, making it one of the most promising candidates for future memory systems. This paper studies the impact of process variations on PCM based on a fast analytical model for determining PCM failure probability. The proposed analytical model takes PCM physical dimensions, programming-current amplitude, and programming duration as inputs and produces the corresponding cell resistance. Whether a PCM cell is functional can be determined by comparing the calculated cell resistance with the reference resistance. We further estimate the overall PCM failure probability and demonstrate strategies on how to minimize memory failures. The proposed model thus provides early stage estimation on memory yield.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114039012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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