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2011 IEEE International SOC Conference最新文献

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Functional verifications for SoC software/hardware co-design: From virtual platform to physical platform SoC软硬件协同设计的功能验证:从虚拟平台到物理平台
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085104
Yi-Li Lin, A. Su
{"title":"Functional verifications for SoC software/hardware co-design: From virtual platform to physical platform","authors":"Yi-Li Lin, A. Su","doi":"10.1109/SOCC.2011.6085104","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085104","url":null,"abstract":"This paper applies heterogeneous simulation to achieve system and functional level co-verification throughout SoC design flow. It reduces high verification complexity resulted from covering software and hardware works and involving various tools. Stubs for data transport and a Verification Router for heterogeneous simulation management are proposed. A functional module is transformed from a highly abstract model to its target design progressively through a series of intermediate models. Those models can be validated as a portion of a complete SoC system model. The proposed heterogeneous verification is demonstrated with a jpeg encoder.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128285117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Power-aware design technique for PAC Duo based embedded system 基于PAC Duo的嵌入式系统功耗感知设计技术
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085134
Shui-An Wen, H. Lin, Chi Wu, Chun-Chin Chen, Kun-Hsien Tsai, Wei-Min Cheng
{"title":"Power-aware design technique for PAC Duo based embedded system","authors":"Shui-An Wen, H. Lin, Chi Wu, Chun-Chin Chen, Kun-Hsien Tsai, Wei-Min Cheng","doi":"10.1109/SOCC.2011.6085134","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085134","url":null,"abstract":"Power consumption has been becoming one of the most important criteria for portable embedded devices. During application program development phase to estimate the power consumption is of great significance. In this paper, we propose a power evaluation methodology for PACDSP instruction set simulator. Programmers can easily observe the power consumption during the application development stage. The power modeling is compared with Synopsys PrimeTime PX, and the maximum deviation is less than 4% by executing the BDTI benchmarks. Furthermore, we also discuss the power consumption of the PAC Duo multimedia platform.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124762022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low power wide tuning range VCO with coupled LC tanks 低功率宽调谐范围VCO与耦合LC油箱
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085075
Shouxian Mou, Kaixue Ma, K. Yeo, N. Mahalingam, Bharatha Kumar Thangarasu
{"title":"A low power wide tuning range VCO with coupled LC tanks","authors":"Shouxian Mou, Kaixue Ma, K. Yeo, N. Mahalingam, Bharatha Kumar Thangarasu","doi":"10.1109/SOCC.2011.6085075","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085075","url":null,"abstract":"A 12GHz VCO fabricated in a 0.18µm SiGe BiCMOS technology with only CMOS devices, is presented. To improve tuning range and phase noise, a technique using strongly magnetic coupled LC tanks with fixed and tunable capacitive elements is proposed. The VCO achieves wide tuning range of 4.3GHz (36%) with only 4.5mW power consumption. The proposed VCO including buffer stage occupies a chip area of 0.17mm2, and can be easily integrated on-chip with other blocks.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126254655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Software defined radio based frequency domain chaotic cognitive radio 基于软件定义无线电的频域混沌认知无线电
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085145
Ruolin Zhou, Xue Li, Jian Zhang, Zhiqiang Wu
{"title":"Software defined radio based frequency domain chaotic cognitive radio","authors":"Ruolin Zhou, Xue Li, Jian Zhang, Zhiqiang Wu","doi":"10.1109/SOCC.2011.6085145","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085145","url":null,"abstract":"Chaotic communication system has attracted strong interests in high security communication due to robustness in multi-path fading environments, resistance to jamming, and low probability of interception. Recently, cognitive radio has emerged as a strong candidate to solve the spectrum congestion problem by operating over under utilized spectrum bands. Hence, it is highly desired to combine the security advantages of chaos communication with cognitive radio to create a chaotic cognitive radio communication system. However, traditional chaotic communication system is based on time-domain chaotic signal generator where the signal occupies one wide contiguous frequency band, making it inappropriate for cognitive radio applications. To apply the chaotic sequence onto cognitive radio to take advantage of multiple spectrum bands, we generate the chaotic signal in frequency domain. By applying a spectrum mask onto the chaotic signal in frequency-domain, a frequency domain non-contiguous chaotic waveform is created. In this paper, we use universal software radio peripheral and GNU radio software to implement and demonstrate a frequency domain chaotic cognitive radio. This demonstration has several unique features: (1) supporting real-time video transmission; (2) taking advantage of multiple non-contiguous spectrum bands; (3) dynamic cognitive radio waveform adaptation according to the primary user transmissions; (4) maintaining the security features of chaotic communication.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129079804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
“Introduction to SoC testing” SoC测试简介
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085153
Laung-Terng Wang
{"title":"“Introduction to SoC testing”","authors":"Laung-Terng Wang","doi":"10.1109/SOCC.2011.6085153","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085153","url":null,"abstract":"Continued advances in manufacturing technology have enabled an SoC design to contain billions of transistors. The increase of circuit complexity has imposed serious challenges on product quality, test cost, and system reliability. In this talk, I will give a brief introduction to SoC testing of digital circuits. Test techniques that have been practiced in industry to improve product quality and test cost are first described. A few emerging techniques to further reduce product development time and increase system reliability are then discussed.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132876111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monitor strategies for variability reduction considering correlation between power and timing variability 考虑功率和时间可变性之间的相关性，监测可变性减少策略
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085081
J. Mauricio, F. Moll, J. Altet
{"title":"Monitor strategies for variability reduction considering correlation between power and timing variability","authors":"J. Mauricio, F. Moll, J. Altet","doi":"10.1109/SOCC.2011.6085081","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085081","url":null,"abstract":"As CMOS technology scales, Process, Voltage and Temperature (PVT) variations have an increasing impact on, performance and power consumption of the electronic devices. Variability causes an undesirable dispersion of performance parameters and a consequent reduction in parametric yield. Monitor and control techniques based on BB and VS can be used to reduce variability. This paper aims to determine which type of sensor provides a better overall variability reduction by taking into account the correlation between different performance magnitudes: static power, dynamic power and delay.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134533331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An analog gamma correction method for high dynamic range applications 高动态范围应用的模拟伽马校正方法
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085112
Yuan Cao, A. Bermak
{"title":"An analog gamma correction method for high dynamic range applications","authors":"Yuan Cao, A. Bermak","doi":"10.1109/SOCC.2011.6085112","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085112","url":null,"abstract":"In this paper, a flexible analog gamma correction technology has been proposed. In order to represent images on modern display systems with proper contrast, gamma correction is required to encode these input images. Conventional gamma corrections are performed in the digital domain. However, due to the limitation of the ADC resolution, the image quality with low level luminance is significantly degraded. In this proposed method, the adjustment of the implementation for the gamma correction in a design flow integrates this image processing with A/D conversion at the same time. By this approach, the quantization noise of the ADC is not amplified by gamma correction. Furthermore, the hardware area and power consumption can be reduced.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127923962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Simultaneous escape routing based on routability-driven net ordering 基于可达性驱动的网络排序的同时逃逸路由
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085100
Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen
{"title":"Simultaneous escape routing based on routability-driven net ordering","authors":"Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen","doi":"10.1109/SOCC.2011.6085100","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085100","url":null,"abstract":"In this paper, given a set of n escape nets between an array of pxq pins and an array of rxs pins, firstly, a routability-driven net order between two given pin arrays is determined for simultaneous escape routing. Furthermore, based on ordered escape routing for two pin arrays, an efficient approach is proposed to solve the routing problem for simultaneous escape routing. Compared with Kong's flow-based approach [11] for three tested examples, the experimental results show that our proposed approach achieves 100% routability for the tested examples and reduces the CPU time by 54.1% on the average.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129339779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits 用于三维集成电路的容错专用NoC拓扑综合
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085088
Y. Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li
{"title":"Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits","authors":"Y. Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li","doi":"10.1109/SOCC.2011.6085088","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085088","url":null,"abstract":"This paper proposes a synthesis methodology for constructing Application-Specific NoCs topology in 3D chips. The multi-cores and communications can be synthesized simultaneously in the system-level floorplanning process with fault tolerant consideration. As a result, the experimental results show that the proposed approach produces 3D NoCs with lower power dissipation than previous works in multimedia applications with relatively small overhead of the number of Through-Silicon-Vias (TSVs) for achieving 100% fault tolerance in 3D NoC links based on single fault assumption.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124294261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a neural recording amplifier with tunable pseudo resistors 带可调伪电阻的神经记录放大器的设计
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085119
Kai-Wen Yao, C. Gong, Shan-Ci Yang, M. Shiue
{"title":"Design of a neural recording amplifier with tunable pseudo resistors","authors":"Kai-Wen Yao, C. Gong, Shan-Ci Yang, M. Shiue","doi":"10.1109/SOCC.2011.6085119","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085119","url":null,"abstract":"This paper describes a voltage-controlled pseudo-resistor with widely available operating voltage range applied to neural recording amplifier designs. The proposed pseudo-resistor which consists of serial-connected PMOS device and an auto-tuning circuit provides ultra-high resistance to cancel DC offset from electrode-electrolyte interface. The proposed design has been estimated in standard CMOS 0.18-µm process, achieving midband gain of 40 dB, bandwidth from 0.4 Hz to 7 kHz, input-referred noise of 5.98 µVrms, calculated NEF of 7.2, and 3.1-µW power consumption.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125633516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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