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A 144-configuration context MEMS optically reconfigurable gate array 一种144组态上下文MEMS光可重构门阵列
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085083
Y. Yamaji, Minoru Watanabe
{"title":"A 144-configuration context MEMS optically reconfigurable gate array","authors":"Y. Yamaji, Minoru Watanabe","doi":"10.1109/SOCC.2011.6085083","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085083","url":null,"abstract":"Demand for space uses of FPGAs is increasing to support hardware repair and hardware update functions in addition to software repair and update functions in spacecraft, satellites, space stations, and other applications. However, under a space radiation environment, the incidence of high-energy charged particles causes single or multi-event latch-up (S/MEL)-associated troubles and single or multi-event upset (S/MEU)-associated temporary failures. Although an FPGA, because of its programmability, presents the advantageous capabilities of recovering from and updating after S/MEL-associated troubles, the FPGA can not guard itself completely from S/MEU-associated temporary failures that might arise on its configuration SRAM. This paper therefore presents a proposal for a 144-configuration context MEMS optically reconfigurable gate array that can support a remotely updatable hardware function, can quickly repair S/MEL-associated permanent failures, and can perfectly guard itself from S/MEU-associated temporary failures that can occur in a space radiation environment.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128454104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon 受经济现象启发的基于多信息素的片上网络路由
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085084
Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, A. Wu
{"title":"Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon","authors":"Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, A. Wu","doi":"10.1109/SOCC.2011.6085084","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085084","url":null,"abstract":"Ant Colony Optimization (ACO) is a collective intelligence problem-solving paradigm. By ACO, we can effectively distribute the central control unit to achieve higher performance. With the scaling of Network-on-Chip (NoC) size, more complex communication problems can severely harm the system performance. Therefore, we need more efficient ACO-adaptive routing to achieve better trend prediction for global load-balancing. In this paper, we introduce a Multi-Pheromone ACO-based (MPACO) routing to make better use of the network information and provide a deeper look to the local model. By adopting the concept of Exponential Moving Average (EMA) in stock market, MPACO provide additional dimension aspect: rate of change in network information by laying pheromone with different evaporation speed. The experimental results show that MPACO can achieve higher performance while maintaining similar implementation cost compared to the previous work.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122888573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessors 聚类分析与遗传算法相结合的微处理器回归套件缩减
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085105
Liucheng Guo, Jiangfang Yi, L. Zhang, Xiaoyin Wang, Dong Tong
{"title":"CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessors","authors":"Liucheng Guo, Jiangfang Yi, L. Zhang, Xiaoyin Wang, Dong Tong","doi":"10.1109/SOCC.2011.6085105","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085105","url":null,"abstract":"Regression testing plays an important role in the simulation-based functional verification of microprocessors. Regression suite is maintained in the entire verification phase with an increase of the scale. However, the executing cost is always high when running the entire suite on a RTL-level simulator. Regression suite reduction (called RSR for short) is presented to reduce the executing cost of the regression suite without debasing the quality of the functional verification. For this two-objective RSR of microprocessors, we present a heuristic algorithm which mainly combines cluster analysis with genetic algorithm (called CGA for short). The experiments on some regression suites at different scales for a microprocessor have shown the efficiency and feasibility of CGA. CGA can effectively reduce about 90% of the executing cost without decreasing the functional coverage in an acceptable runtime.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131158363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Instruction set customization for area-constrained FPGA designs 区域受限FPGA设计的指令集定制
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085114
Alok Prakash, S. Lam, C. Clarke, T. Srikanthan
{"title":"Instruction set customization for area-constrained FPGA designs","authors":"Alok Prakash, S. Lam, C. Clarke, T. Srikanthan","doi":"10.1109/SOCC.2011.6085114","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085114","url":null,"abstract":"Custom instructions are commonly used to meet the strict design constraints in high performance systems. This paper extends the application space of our previously proposed FPGA-aware custom instruction enumeration and selection technique for area-constrained designs that maximizes the logic utilization of the available FPGA space. Results indicate a factor of 4 improvement in cycle savings over conventional selection techniques and an average runtime reduction of over 31% and 50% in the enumeration and selection phases respectively.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127792735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Well tapping methodologies in power-gating design 电源门控设计中的攻丝方法
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085133
K. Shi, D. Tester
{"title":"Well tapping methodologies in power-gating design","authors":"K. Shi, D. Tester","doi":"10.1109/SOCC.2011.6085133","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085133","url":null,"abstract":"65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production power-gating designs considering design schedule, leakage power, chip area and complexity.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133313321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power-aware design technique for PAC Duo based embedded system 基于PAC Duo的嵌入式系统功耗感知设计技术
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085134
Shui-An Wen, H. Lin, Chi Wu, Chun-Chin Chen, Kun-Hsien Tsai, Wei-Min Cheng
{"title":"Power-aware design technique for PAC Duo based embedded system","authors":"Shui-An Wen, H. Lin, Chi Wu, Chun-Chin Chen, Kun-Hsien Tsai, Wei-Min Cheng","doi":"10.1109/SOCC.2011.6085134","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085134","url":null,"abstract":"Power consumption has been becoming one of the most important criteria for portable embedded devices. During application program development phase to estimate the power consumption is of great significance. In this paper, we propose a power evaluation methodology for PACDSP instruction set simulator. Programmers can easily observe the power consumption during the application development stage. The power modeling is compared with Synopsys PrimeTime PX, and the maximum deviation is less than 4% by executing the BDTI benchmarks. Furthermore, we also discuss the power consumption of the PAC Duo multimedia platform.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124762022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Software defined radio based frequency domain chaotic cognitive radio 基于软件定义无线电的频域混沌认知无线电
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085145
Ruolin Zhou, Xue Li, Jian Zhang, Zhiqiang Wu
{"title":"Software defined radio based frequency domain chaotic cognitive radio","authors":"Ruolin Zhou, Xue Li, Jian Zhang, Zhiqiang Wu","doi":"10.1109/SOCC.2011.6085145","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085145","url":null,"abstract":"Chaotic communication system has attracted strong interests in high security communication due to robustness in multi-path fading environments, resistance to jamming, and low probability of interception. Recently, cognitive radio has emerged as a strong candidate to solve the spectrum congestion problem by operating over under utilized spectrum bands. Hence, it is highly desired to combine the security advantages of chaos communication with cognitive radio to create a chaotic cognitive radio communication system. However, traditional chaotic communication system is based on time-domain chaotic signal generator where the signal occupies one wide contiguous frequency band, making it inappropriate for cognitive radio applications. To apply the chaotic sequence onto cognitive radio to take advantage of multiple spectrum bands, we generate the chaotic signal in frequency domain. By applying a spectrum mask onto the chaotic signal in frequency-domain, a frequency domain non-contiguous chaotic waveform is created. In this paper, we use universal software radio peripheral and GNU radio software to implement and demonstrate a frequency domain chaotic cognitive radio. This demonstration has several unique features: (1) supporting real-time video transmission; (2) taking advantage of multiple non-contiguous spectrum bands; (3) dynamic cognitive radio waveform adaptation according to the primary user transmissions; (4) maintaining the security features of chaotic communication.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129079804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Monitor strategies for variability reduction considering correlation between power and timing variability 考虑功率和时间可变性之间的相关性，监测可变性减少策略
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085081
J. Mauricio, F. Moll, J. Altet
{"title":"Monitor strategies for variability reduction considering correlation between power and timing variability","authors":"J. Mauricio, F. Moll, J. Altet","doi":"10.1109/SOCC.2011.6085081","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085081","url":null,"abstract":"As CMOS technology scales, Process, Voltage and Temperature (PVT) variations have an increasing impact on, performance and power consumption of the electronic devices. Variability causes an undesirable dispersion of performance parameters and a consequent reduction in parametric yield. Monitor and control techniques based on BB and VS can be used to reduce variability. This paper aims to determine which type of sensor provides a better overall variability reduction by taking into account the correlation between different performance magnitudes: static power, dynamic power and delay.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134533331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
“Introduction to SoC testing” SoC测试简介
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085153
Laung-Terng Wang
{"title":"“Introduction to SoC testing”","authors":"Laung-Terng Wang","doi":"10.1109/SOCC.2011.6085153","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085153","url":null,"abstract":"Continued advances in manufacturing technology have enabled an SoC design to contain billions of transistors. The increase of circuit complexity has imposed serious challenges on product quality, test cost, and system reliability. In this talk, I will give a brief introduction to SoC testing of digital circuits. Test techniques that have been practiced in industry to improve product quality and test cost are first described. A few emerging techniques to further reduce product development time and increase system reliability are then discussed.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132876111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra low power QC-LDPC decoder with high parallelism 具有高并行性的超低功耗QC-LDPC解码器
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085136
Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Y. Lu, Dajiang Zhou, S. Goto
{"title":"Ultra low power QC-LDPC decoder with high parallelism","authors":"Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Y. Lu, Dajiang Zhou, S. Goto","doi":"10.1109/SOCC.2011.6085136","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085136","url":null,"abstract":"This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 8∼16 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5× higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114850373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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