2011 IEEE International SOC Conference最新文献_第2页

A 144-configuration context MEMS optically reconfigurable gate array 一种144组态上下文MEMS光可重构门阵列

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085083

Y. Yamaji, Minoru Watanabe

引用次数: 4

Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon 受经济现象启发的基于多信息素的片上网络路由

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085084

Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, A. Wu

引用次数: 4

CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessors 聚类分析与遗传算法相结合的微处理器回归套件缩减

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085105

Liucheng Guo, Jiangfang Yi, L. Zhang, Xiaoyin Wang, Dong Tong

引用次数: 2

Instruction set customization for area-constrained FPGA designs 区域受限FPGA设计的指令集定制

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085114

Alok Prakash, S. Lam, C. Clarke, T. Srikanthan

引用次数: 2

Well tapping methodologies in power-gating design 电源门控设计中的攻丝方法

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085133

K. Shi, D. Tester

引用次数: 3

A silicon core for an acoustic archival tag 用于声学档案标签的硅芯

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085097

G. Fischer, H. Rossby

引用次数: 3

Ultra low power QC-LDPC decoder with high parallelism 具有高并行性的超低功耗QC-LDPC解码器

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085136

Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Y. Lu, Dajiang Zhou, S. Goto

引用次数: 12

A novel methodology for Multi-Project System-on-a-Chip 多项目单片系统的一种新方法

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085090

Chih-Chyau Yang, N. Chang, Shih-Lun Chen, Wei-De Chien, Chi-Shi Chen, Chien‐Ming Wu, Chun-Ming Huang

{"title":"A novel methodology for Multi-Project System-on-a-Chip","authors":"Chih-Chyau Yang, N. Chang, Shih-Lun Chen, Wei-De Chien, Chi-Shi Chen, Chien‐Ming Wu, Chun-Ming Huang","doi":"10.1109/SOCC.2011.6085090","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085090","url":null,"abstract":"In this paper, a novel silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. For integrating heterogeneous SoC projects into a single chip, the current SoC methodology is insufficient due to the complexity of MP-SoC. In order to improve the robustness of MP-SoC design and verification, a new design flow was developed. It consists of a virtual platform, a logical implementation, a rapid prototyping platform, a physical implementation, and testing stages. The virtual platform is a system modeling and hardware/software co-design system by using electronic system level (ESL). VIP system is adopted for the AMBA-compliant check of the interfaces of the MP-SoC. In addition, STEAC and DFT were used to facilitate MP-SoC testing integration. The rapid prototyping platform called “CONCORD” which has characteristics of connection flexibility, modularization, and consistence architecture for emulating the hardware of MP-SoC before chip being taped out. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with ten SoC projects sharing the common platform. The total silicon area is about 37.97mm2 in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area 129.39mm2 by implementing these projects separately, the results show that there are 91.42 mm2 or 70.6 % silicon area reduced by this novel silicon prototyping methodology.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow 模拟电路的参数化DFM解决方案:电驱动的热点检测、分析和校正流程

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085082

R. Salem, A. Arafa, Sherif Hany, Abdelrahman ElMously, H. Eissa, M. Dessouky, D. Nairn, M. Anis

{"title":"A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow","authors":"R. Salem, A. Arafa, Sherif Hany, Abdelrahman ElMously, H. Eissa, M. Dessouky, D. Nairn, M. Anis","doi":"10.1109/SOCC.2011.6085082","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085082","url":null,"abstract":"As VLSI technology pushes into advanced nodes, designers and foundries have exposed a hitherto insignificant set of yield problems. To combat yield failures, the semiconductor industry has deployed new tools and methodologies commonly referred to as design for manufacturing (DFM). Most of the early efforts concentrated on catastrophic failures, or physical DFM problems. Recently, there has been an increased emphasis on parametric yield issues, referred to as electrical-DFM (e-DFM). In this paper, we present a complete electrical-aware design for manufacturing solution that detects, analyzes, and fixes electrical hotspots (e-hotspots) caused by different process variations within the analog circuit design. Novel algorithms are proposed to implement the engines that are used to develop this solution. Our proposed flow is examined on a 65nm industrial voltage control oscillator (VCO). E-hotspot devices with 5.5% variation in DC current are identified. After fixing the e-hotspots, the DC current variation in these devices is reduced to 0.9%, while saving the original VCO specifications.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123907874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Low power Gm-boosted differential Colpitts VCO 低功耗通用升压差动科尔匹压控振荡器

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085109

Yi-Pei Su, Wei-Yi Hu, Jia-Wei Lin, Yun-Chung Chen, S. Sezer, Sao-Jie Chen

引用次数: 8