Ultra low power QC-LDPC decoder with high parallelism

Abstract

This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 8∼16 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5× higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.