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2011 IEEE International SOC Conference最新文献

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Keynote speaker 主讲人
2011 IEEE International SOC Conference Pub Date : 2022-10-13 DOI: 10.1109/ths.2010.5655228
Y. Patt
{"title":"Keynote speaker","authors":"Y. Patt","doi":"10.1109/ths.2010.5655228","DOIUrl":"https://doi.org/10.1109/ths.2010.5655228","url":null,"abstract":"SoCC started out as the IEEE ASIC Conference, moved to ASIC/SOC, and then to its current title SoCC. As the number of transistors on a chip has increased, designers have found it useful to include, in addition to the processor, a lot of system stuff that is in many ways orthogonal to the processor. We will soon reach the point where each chip will contain 50 billion transistors. Even after we take into account all the system stuff, there will still be a huge number of transistors available for our use. How do we harness them? The trend so far has been to increase the number of processor cores? I submit that there is a better way: the return of the ASIC. In this talk I will discuss why the ASIC will be particularly important for the microprocessor of 2020, and what we must do differently between now and then if we are to effectively exploit ASICs to the benefit of high performance chips.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132490986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than moore 数字微流控生物芯片的设计和优化方法:功能多样性和超越摩尔的愿景
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085141
K. Chakrabarty
{"title":"Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than moore","authors":"K. Chakrabarty","doi":"10.1109/SOCC.2011.6085141","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085141","url":null,"abstract":"Microfluidics-based biochips (or lab-on-chip) are revolutionizing laboratory procedures in molecular biology, and leading to a convergence of information technology with biochemistry and nanoelectronics. Advances in microfluidics technology offer exciting possibilities for high-throughput DNA sequencing, protein crystallization, drug discovery, immunoassays, neo-natal and point-of-care clinical diagnostics, etc. As microfluidic lab-on-chip mature into multifunctional devices with “smart” reconfiguration and adaptation capabilities, automated design and ease of use become extremely important. Computer-aided design (CAD) tools are needed to allow designers and users to harness the new technology that is rapidly emerging for integrated biofluidics. This talk will present ongoing work at Duke University on design automation techniques for microfluidic biochips. First, the speaker will provide an overview of electrowetting-based digital microfluidic biochips. Next, the speaker will describe synthesis tools that can map bioassay protocols to a reconfigurable microfluidic device and generate control software, an optimized schedule of bioassay operations, the binding of assay operations to functional units, and the layout and droplet flow-paths for the biochip. Techniques for pin-constrained chip design, fault detection, and dynamic reconfiguration will also be presented. An automated design flow allows the biochip user to concentrate on the development of nano- and micro-scale bioassays, leaving implementation details to CAD tools.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116759492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Concept and design of exhaustive-parallel search algorithm for Network-on-Chip 片上网络穷举并行搜索算法的概念与设计
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085123
Meganathan Deivasigamani, Shaghayegh Tabatabaei, Naveed Ul Mustafa, H. Ijaz, Haris Bin Aslam, Shaoteng Liu, A. Jantsch
{"title":"Concept and design of exhaustive-parallel search algorithm for Network-on-Chip","authors":"Meganathan Deivasigamani, Shaghayegh Tabatabaei, Naveed Ul Mustafa, H. Ijaz, Haris Bin Aslam, Shaoteng Liu, A. Jantsch","doi":"10.1109/SOCC.2011.6085123","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085123","url":null,"abstract":"This paper presents the concept and design of exhaustive-parallel search algorithm for Network-on-Chip. The proposed parallel algorithm searches minimal path between source and destination in a forward-wave-propagation manner. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The NoC fabric is designed for 8×8 mesh architecture and its performance is evaluated.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120931945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On-demand memory sub-system for multi-core SoCs 多核soc的按需存储器子系统
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085132
Po-Tsang Huang, Yu-ning Chang, W. Hwang
{"title":"On-demand memory sub-system for multi-core SoCs","authors":"Po-Tsang Huang, Yu-ning Chang, W. Hwang","doi":"10.1109/SOCC.2011.6085132","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085132","url":null,"abstract":"For heterogeneous multi-core SoCs, the increasing demand of the memory capacity and bandwidth becomes a critical design challenge. In this paper, an on-demand memory sub-system is presented to efficiently control the memory access and memory resource allocation using adaptively allocated cache memory. The proposed adaptively allocated cache memory can dynamically assign a variable number of SRAM banks for process elements (PEs) to optimize the utilization of the centralized on-chip cache. In a wireless video entertainment system, a 7.13% execution time reduction and 10.53% energy reduction of memories can be achieved using the adaptively allocated cache memory.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121766138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system 一种用于10GB/S背板通信系统的简化信号馈通6分接预强调电路
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085130
Harry Tai, P. Noel, T. Kwasniewski
{"title":"A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system","authors":"Harry Tai, P. Noel, T. Kwasniewski","doi":"10.1109/SOCC.2011.6085130","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085130","url":null,"abstract":"The current mode digital-to-analog converter (iDAC) has been widely used in finite-impulse response (FIR) filter implementations as it is well-suited for high-speed operation. This paper proposes a novel solution to reduce the signal feed-through problem commonly encountered in current mode digital-to-analog converters in pre-emphasis circuits. To improve the eye opening, the circuit must be able to limit the flow of feed-through signal to the summing node. The proposed multi-tap pre-emphasis circuit has been simulated using an IBM 130nm CMOS technology.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131381310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system 基于模糊控制系统的VLIW体系结构的代码优化与硬件探索相结合
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085072
Xiaoyan Jia, G. Fettweis
{"title":"Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system","authors":"Xiaoyan Jia, G. Fettweis","doi":"10.1109/SOCC.2011.6085072","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085072","url":null,"abstract":"The Synchronous Transfer Architecture is a low power architecture of VLIW processor, which enables the direct data routing through buffered output ports of functional units. To improve the system efficiency of STA, in this paper we propose a novel approach to integrate compiler techniques with architecture exploration: A fuzzy control system is implemented to help the compiler back-end determine the optimal configuration of the STA processor and the corresponding target VLIW for different applications. This approach achieves the integration of the optimizations of code generation and hardware design. According to our studies, the drop in execution time is between 18% and 43% compared to the compiled ARM assembly code. Up to 42.4% register read and 67.9% register write operations are cut down on average. Except for reding the input data and writing back the results, all the other memory accesses for ARM architecture are avoided, giving us a dramatic reduction in the power consumption. Finally, the novel approach enjoys short compilation time and less complex implementation.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133158050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Floorplanning challenges in early chip planning 平面规划在早期芯片规划中的挑战
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085096
Jeonghee Shin, J. Darringer, Guojie Luo, M. Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy
{"title":"Floorplanning challenges in early chip planning","authors":"Jeonghee Shin, J. Darringer, Guojie Luo, M. Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy","doi":"10.1109/SOCC.2011.6085096","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085096","url":null,"abstract":"Early chip planning is becoming more critical as server system designers strive to explore a large design space with multiple cores and accelerators in an advanced silicon technology that includes 3D chip stacking. During early chip planning, designers search for the high-level design and layout that best satisfies a myriad of constraints and targets. In this paper, we discuss our experience in applying traditional floorplanning tools at this early stage and suggest how they might be adapted for early floorplanning.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131325234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips 解缓存:一种新的基于大规模NoC的多处理器片上系统缓存方案
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085079
A. Sanusi, M. Bayoumi
{"title":"De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips","authors":"A. Sanusi, M. Bayoumi","doi":"10.1109/SOCC.2011.6085079","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085079","url":null,"abstract":"Multi-level caches are used in multiprocessor systems to exploit locality of data and decrease the bandwidth demands on the network. Apart from exploiting locality in large-scale networks, we must also amortize the cost of distant communication so as to reduce memory request latency which is a critical determinant of multiprocessor performance. Our proposed architecture called the De-Cache ($De) architecture exploits the nature of the network-on-chip (NoC) structure by introducing what we called detour caches to store data from the most distant physical memory locations closer to the requesting node. Our experiments show that by using our proposed $De architecture we can decrease the memory request latency up to approximately 29.0% with very little degradation to the network performance.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116274694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture 蜂窝:多粒度动态可重构运行时自适应硬件架构
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085115
Alexander Thomas, Michael Rückauer, J. Becker
{"title":"HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture","authors":"Alexander Thomas, Michael Rückauer, J. Becker","doi":"10.1109/SOCC.2011.6085115","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085115","url":null,"abstract":"Reconfigurable computing is a promising concept for data processing. Higher parallel utilization of the given hardware resources results in better performance and lower power consumption compared to conventional approaches like von Neumann or Harvard architectures. Nevertheless, current reconfigurable solutions have their limitations and require more scientific attention. This contribution presents a new reconfigurable architecture which targets many weaknesses like array utilization, reusability and post-compile flexibility. Therefore, new features like runtime routing, multi-grained data types, partial reconfiguration and application tailored adaptability have been implemented and tightly coupled to software tools and programming languages. A demonstration chip using TSMC 90nm standard cell technology has been designed and is currently in production.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124633019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Baseband signal processing in SDR SDR中的基带信号处理
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085144
T. Chiueh
{"title":"Baseband signal processing in SDR","authors":"T. Chiueh","doi":"10.1109/SOCC.2011.6085144","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085144","url":null,"abstract":"Wireless communications free users from being attached to wires and allow them to remain connected even when they move around at home or are on the road. Services that support high throughput yet cost little or even nothing are attractive to the consumers. Today, Code-Division Multiple Access (CDMA) technology makes up the foundation of 3G cellular system and Global Positioning System (GPS). Many other wireless standards are based on multi-carrier modulation technology (specifically OFDM). Multi-carrier modulation technology enjoys flexible spectral resource allocation and management as well as easy equalization. On the other hand, antenna array and spatial MIMO processing, which have been around for several decades, can provide spatial diversity gain and/or channel capacity increase. The application of the MIMO technology to wireless communications takes place only recently, exemplified by its adoption in IEEE 802.11n, IEEE 802.16e, and 3GPP LTE. In this talk I will address the above three important baseband technologies using insightful illustrations. In addition, I will give a design example using our previous work on software GPS receiver.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129692678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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