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2011 IEEE International SOC Conference最新文献

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A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations 一种基于工艺变化下小信号模型的模拟电路性能影响估计方法
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085098
Po-Yu Kuo, Siwat Saibua, Dian Zhou
{"title":"A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations","authors":"Po-Yu Kuo, Siwat Saibua, Dian Zhou","doi":"10.1109/SOCC.2011.6085098","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085098","url":null,"abstract":"Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number of simulation runs. This paper proposes a novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. The accuracy of the small signal model has been verified with CMOS circuit. The proposed approach has been demonstrated by a CMOS two-stage operational transconductance amplifier (OTA). To achieve an accurate estimate, the modified small signal model which consider more parasitic capacitors in CMOS transistor, has been applied in the proposed approach. By applying the proposed approach based on optimization method, the upper and lower bounds of magnitude and phase, can be evaluated accurately in much less computation time compared to Monte Carlo simulations. All experimental results are carried out using a standard 0.35-µm CMOS process technology.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128967139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low power tri-state register files design for modern out-of-order processors 现代乱序处理器的低功耗三态寄存器文件设计
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085113
Na Gong, Geng Tang, Jinhui Wang, R. Sridhar
{"title":"Low power tri-state register files design for modern out-of-order processors","authors":"Na Gong, Geng Tang, Jinhui Wang, R. Sridhar","doi":"10.1109/SOCC.2011.6085113","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085113","url":null,"abstract":"In this paper, we propose a novel integrated circuit and architectural level technique to reduce power consumption of register files in high-performance microprocessors. Our simulation results on 32-nm process show 12.7–14.1% power reduction for ROB (Reorder Buffer)-based microprocessors and 12.4–17.9% power reduction for checkpoint-based microprocessors, respectively, with less than 5% impact on excess time.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129278861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuit 一种紧凑的延迟回收时钟偏斜补偿和/或占空比校正电路
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085073
Yi-Ming Wang, Jen-Tsung Yu, Y. Surya, Chung-Hsun Huang
{"title":"A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuit","authors":"Yi-Ming Wang, Jen-Tsung Yu, Y. Surya, Chung-Hsun Huang","doi":"10.1109/SOCC.2011.6085073","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085073","url":null,"abstract":"A clock skew-compensation and/or duty-cycle-correction circuit (CSADC) is indispensably required to maximize the performance of a synchronous double edge clocking system. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more design complexity. A compact delay-recycled CSADC is proposed in this work. Compared to conventional CSADCs, the proposed circuit achieves at least a 2.5 times reduction in lock-in cycles, a 5.49 times reduction in power, and a 3.67 times reduction in power bandwidth ratio.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130342858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Recent research and emerging challenges in design and optimization for digital microfluidic biochips 数字微流控生物芯片设计与优化的最新研究与挑战
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085143
Tsung-Wei Huang, Yan-You Lin, Jia-Wen Chang, Tsung-Yi Ho
{"title":"Recent research and emerging challenges in design and optimization for digital microfluidic biochips","authors":"Tsung-Wei Huang, Yan-You Lin, Jia-Wen Chang, Tsung-Yi Ho","doi":"10.1109/SOCC.2011.6085143","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085143","url":null,"abstract":"Advances in droplet-based digital microfluidic biochips (DMFBs) have led to the emergence of biochips for automating laboratory procedures in biochemistry and molecular biology. These devices enable the precise control of microliter of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and integrate various bioassay operations, such as sample preparation, analysis, separation, and detection. To meet the challenges of increasing design complexity, computer-aided-design (CAD) tools have been involved to build DMFBs efficiently. This paper provides an overview of DMFBs and describes emerging CAD tools for the automated synthesis and optimization of DMFB designs, from fluidic-level synthesis to chip-level design. Design automations are expected to relieve the design burden of manual optimization of bioassays, time-consuming chip designs, and costly testing and maintenance procedures. With the assistance of CAD tools, users can concentrate on the development and abstraction of nanoscale bioassays while leaving chip optimization and implementation details to CAD tools.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131259714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low power 120 KSPS 12bit SAR ADC with a novel switch control method for internal CDAC 低功耗120 KSPS 12位SAR ADC，内部CDAC采用新颖的开关控制方法
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085099
Abhisek Dey, T. K. Bhattacharyya
{"title":"Low power 120 KSPS 12bit SAR ADC with a novel switch control method for internal CDAC","authors":"Abhisek Dey, T. K. Bhattacharyya","doi":"10.1109/SOCC.2011.6085099","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085099","url":null,"abstract":"A low power 1.3V 12bit successive approximation register analog-to-digital converter (SAR ADC) is presented for MEMS and biomedical applications. In the DAC of this ADC, a new switch control technique has been proposed to make the ADC more energy as well as area efficient. Besides, a very high resolution, low offset CMOS comparator is designed for the satisfactory operation of the ADC. The complete ADC has been implemented using UMC 0.18µm RF/CMOS process with 1.8V supply voltage and 1.3V reference voltage for the DAC. Its performance has been verified by spectre simulation. The ADC achieved a sampling rate of 120KSPS and a power consumption of 3mW at 1.8V supply voltage. Its DNL and INL are 0.68LSB and 0.7LSB respectively.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121078520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A low-power all-digital phase modulator pair for LINC transmitters 用于LINC发射机的低功率全数字相位调制器对
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085074
Ping-Yuan Tsai, Tsan-Wen Chen, Chen-Yi Lee
{"title":"A low-power all-digital phase modulator pair for LINC transmitters","authors":"Ping-Yuan Tsai, Tsan-Wen Chen, Chen-Yi Lee","doi":"10.1109/SOCC.2011.6085074","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085074","url":null,"abstract":"This paper presents a low-power all-digital phase modulator (PM) pair to generate constant-envelope signals for LINC transmitters. To reduce the power overhead, an open-loop delay line based phase shifter with a continuous locking scheme is adopted for the PM design. This design is implemented by 90 nm CMOS technology with active area of 0.1892 mm2. The PM provides 8-bit resolution with RMS error 0.33° at IF frequency 80 MHz, and the power consumption is only 885 uW with 1.0 V supply voltage. Considering a 64-QAM OFDM system, the EVM of −31.87 dB can be achieved by using the proposed PM pair.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127156361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A multi-segment clocking scheme to reduce on-chip EMI 一个多段时钟方案，以减少片上电磁干扰
2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085110
B. Mesgarzadeh, I. Zadeh, A. Alvandpour
{"title":"A multi-segment clocking scheme to reduce on-chip EMI","authors":"B. Mesgarzadeh, I. Zadeh, A. Alvandpour","doi":"10.1109/SOCC.2011.6085110","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085110","url":null,"abstract":"This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127367005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The pending arrival of Phase Change Memory: The implications on the memory-storage hierarchy and on future systems development 即将到来的相变存储器:对存储器-存储层次结构和未来系统发展的影响
2011 IEEE International SOC Conference Pub Date : 2011-09-01 DOI: 10.1109/SOCC.2011.6085095
S. Chiras
{"title":"The pending arrival of Phase Change Memory: The implications on the memory-storage hierarchy and on future systems development","authors":"S. Chiras","doi":"10.1109/SOCC.2011.6085095","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085095","url":null,"abstract":"Phase Change Memory (PCM) technology has been explored for decades, yet today it is looming on the verge of market impact. Commercially available today for very specific applications, the full scope of value remains to be realized, or even defined. PCM offers unique capabilities and features not seen in any other commercial memory or storage technology, yet its immaturity in a well established marketplace makes adoption in the server space challenging. Full utilization will depend not only upon advancements in PCM density and improvements in performance, but also more fundamental changes in the age old DRAM to disk hierarchy and adoption of a new paradigm in how system architecture is approached - technology/system/application co-development. In the age of systems optimized for specific workloads, truly exploiting the value of PCM will depend upon optimizations being made across the entire system stack, from the technology itself, to the system architecture, and in the software stack.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123972908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plenary speaker 全体人
2011 IEEE International SOC Conference Pub Date : 1900-01-01 DOI: 10.1109/socc.2011.6085139
Chih-Kung Lee
{"title":"Plenary speaker","authors":"Chih-Kung Lee","doi":"10.1109/socc.2011.6085139","DOIUrl":"https://doi.org/10.1109/socc.2011.6085139","url":null,"abstract":"Ageing population and decreasing birth rates are common phenomena taking place around the world. These two factors have increased the rise of chronic diseases and have led to uneven distribution of medical resources as well as the emergence of basic health care demands in emerging markets. Looking forth to the future, it is projected that telecare will become a major means of coping with such issues. According to forecasts by various research institutes, the global telecare market is expected to see an annual 20% growth rate over the coming years. In Gartner's Hype Cycle for Telemedicine, 2010 Report, mobile health monitoring and home health monitoring are listed as highly anticipated health care applications for the future and which will require advanced integration of information and communication technologies.The medical electronics industry has been booming in recent years. With the maturation of wireless LAN (Local Area Network), Bluetooth low energy, and ZigBee technologies, it is projected that medical electronic devices will see further development in wireless connectivity, thereby providing dedicated, stable, and low-cost telecare services for the people. With its strong infrastructure and technological capability, the Taiwanese ICT industry is expected to provide ideal support for the development of telecare. Due to the vigorous involvement of the government and the industry, it is forecasted that the Taiwanese telecare industry will reach approximately US$18 billion in 2015. This speech will analyze the global development trends of telecare and address the applications, opportunities, and future outlook for the biomedical electronics and related industries in Taiwan.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131641451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plenary speaker 全体人
2011 IEEE International SOC Conference Pub Date : 1900-01-01 DOI: 10.1109/socc.2011.6085138
G. De Micheli
{"title":"Plenary speaker","authors":"G. De Micheli","doi":"10.1109/socc.2011.6085138","DOIUrl":"https://doi.org/10.1109/socc.2011.6085138","url":null,"abstract":"Nanosystems - based on the systematic application of nano-technologies - will create a large market of applications and a renewed perspective for electronic design and manufacturing companies. Such systems will be the fundamental building blocks of wearable and ambient systems, to gather and integrate heretogeneous data in real time and to operate and communicate in a wireless and ultra low power mode. The design of these systems will be enabled by the hybridization of manufacturing technologies to attain unprecedented levels performance as well as to diversify applications by means of integrated circuits and sensors. To accomplish this ambitious goal, new technologies and architectures must be matched and tailored to the operational environment by solving novel challenging design and optimization problems, through the creation of novel design methodologies and tools.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127711157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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