2011 IEEE International SOC Conference最新文献_第7页

A register-transfer level testability analyzer 一个寄存器传输级可测试性分析器

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085107

Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin

引用次数: 0

TSV sharing through multiplexing for TSV count minimization in high-level synthesis 在高级合成中通过多路复用实现TSV计数最小化的TSV共享

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085124

Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang

引用次数: 10

Fair rate packet arbitration in Network-on-Chip 片上网络中的公平速率分组仲裁

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085085

F. Guderian, E. Fischer, M. Winter, G. Fettweis

引用次数: 15

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control 高性能低VMIN 55nm 512Kb无扰动8T SRAM，具有自适应VVSS控制

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085080

Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, C. Chuang, W. Hwang, S. Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, C. Hsu

引用次数: 6

VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes 准循环LDPC码的区域高效存储器访问体系结构的VLSI设计

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085108

Ming-Der Shieh, Shih-Hao Fang, Shing-Chung Tang, Der-Wei Yang

引用次数: 0

Compiler-assisted technique for rapid performance estimation of FPGA-based processors 基于fpga处理器的快速性能评估的编译器辅助技术

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085116

Y. Aung, S. Lam, T. Srikanthan

引用次数: 6

“Manufacturing test of systems-on-a-chip (SoCs)” 片上系统(soc)的制造测试

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085148

J. Abraham

引用次数: 1

Recent research and emerging challenges in the System-Level Design of digital microfluidic biochips 数字微流控生物芯片系统级设计的最新研究和新挑战

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085142

P. Pop, E. Maftei, J. Madsen

{"title":"Recent research and emerging challenges in the System-Level Design of digital microfluidic biochips","authors":"P. Pop, E. Maftei, J. Madsen","doi":"10.1109/SOCC.2011.6085142","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085142","url":null,"abstract":"Microfluidic biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the basic functions for biochemical analysis. The “digital” biochips are manipulating liquids not as a continuous flow, but as discrete droplets on a two-dimensional array of electrodes. Basic microfluidic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a series of electrodes. The challenges facing biochips are similar to those faced by microelectronics some decades ago. Computer-Aided Design tools for microfluidics are in their infancy, and designers are currently using manual, bottom-up design approaches to implement such biochips. Considering their architecture and the design tasks that have to be performed, the design of digital biochips has similarities to the high-level synthesis of integrated circuits. Motivated by this similarity, a few researchers have recently started to propose approaches for the top-down design of biochips. So far, they have assumed that operations are executing on virtual modules of rectangular shape, formed by grouping adjacent electrodes, and which have a fixed placement on the array. However, operations can actually execute by routing the droplets on any sequence of electrodes on the biochip. In this paper, we outline the original module-based synthesis problem, and then we present recent work which eliminates the concept of virtual modules and allows droplets to move on the chip on any route during operation execution. We discuss the advantages of such an approach, and identify the challenges and opportunities of system-level design of digital microfluidic biochips.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114865645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Computation and communication aware run-time mapping for NoC-based MPSoC platforms 基于noc的MPSoC平台的计算和通信感知运行时映射

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085078

S. Kaushik, Ashutosh Kumar Singh, T. Srikanthan

{"title":"Computation and communication aware run-time mapping for NoC-based MPSoC platforms","authors":"S. Kaushik, Ashutosh Kumar Singh, T. Srikanthan","doi":"10.1109/SOCC.2011.6085078","DOIUrl":"https://doi.org/10.1109/SOCC.2011.6085078","url":null,"abstract":"Design-time strategies are suited only for mapping predefined set of applications and thus cannot predict dynamic behavior incurred due to the target applications and state of the platform at run-time. This dynamism demands run-time mapping of application tasks to maintain a critical balance between performance and resource optimization. Any disturbance may either lead to digression from expected performance or complete drain of valuable resources. So, it becomes mandatory to devise algorithms which can intelligently distribute the application tasks among processors taking communication overhead, computation load and resource utilization in consideration. This paper proposes a heuristic that illustrates how to incorporate these factors for mapping multiple tasks onto MPSoC platforms, where communication takes place through a Network-on-Chip. The heuristic attempts to balance the processing load on the platform processing elements (PEs) while reducing communication overhead by mapping highly communicating tasks on the same PE. For MPEG-4 application, the proposed technique reduces total execution time by 33%, resource usage by 37% and energy consumption by 40% when compared to state-of-the-art run-time mapping techniques.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115729856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions 一种节能的10T基于sram的FIFO存储器，工作在近/亚阈值区域

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI: 10.1109/SOCC.2011.6085069

Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, W. Hwang

引用次数: 4