一个寄存器传输级可测试性分析器

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI:10.1109/SOCC.2011.6085107

Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin

{"title":"一个寄存器传输级可测试性分析器","authors":"Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin","doi":"10.1109/SOCC.2011.6085107","DOIUrl":null,"url":null,"abstract":"This paper presents a statistic-based method to estimate the testability of a design at Register-Transfer Level. This testability estimation technique is composed of a new proposed high-level design representation and a Monte Carlo simulation which exploits a statistic model to bound the error rate and confidence level of simulation results. The experimental results show that the proposed method can efficiently report more than 60% hard-to-test points of an RL design on average prior to the synthesis task.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A register-transfer level testability analyzer\",\"authors\":\"Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin\",\"doi\":\"10.1109/SOCC.2011.6085107\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a statistic-based method to estimate the testability of a design at Register-Transfer Level. This testability estimation technique is composed of a new proposed high-level design representation and a Monte Carlo simulation which exploits a statistic model to bound the error rate and confidence level of simulation results. The experimental results show that the proposed method can efficiently report more than 60% hard-to-test points of an RL design on average prior to the synthesis task.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085107\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085107","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了一种基于统计的方法来估计一个设计在寄存器-传输级别的可测试性。这种可测试性估计技术是由一种新的高级设计表示和蒙特卡罗仿真组成的，蒙特卡罗仿真利用统计模型来约束仿真结果的错误率和置信水平。实验结果表明，该方法在合成任务前平均可以有效地报告60%以上的RL设计的难以测试点。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A register-transfer level testability analyzer

This paper presents a statistic-based method to estimate the testability of a design at Register-Transfer Level. This testability estimation technique is composed of a new proposed high-level design representation and a Monte Carlo simulation which exploits a statistic model to bound the error rate and confidence level of simulation results. The experimental results show that the proposed method can efficiently report more than 60% hard-to-test points of an RL design on average prior to the synthesis task.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2011 IEEE International SOC Conference

自引率

0.00%

发文量