{"title":"基于fpga处理器的快速性能评估的编译器辅助技术","authors":"Y. Aung, S. Lam, T. Srikanthan","doi":"10.1109/SOCC.2011.6085116","DOIUrl":null,"url":null,"abstract":"This paper proposes a compiler-assisted technique to rapidly estimate performance of a wide range of FPGA processors without requiring actual execution on target processor or ISS. Experimental results show that this technique estimates performance of a widely-used FPGA processor with an average error of 2% in the order of seconds.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Compiler-assisted technique for rapid performance estimation of FPGA-based processors\",\"authors\":\"Y. Aung, S. Lam, T. Srikanthan\",\"doi\":\"10.1109/SOCC.2011.6085116\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a compiler-assisted technique to rapidly estimate performance of a wide range of FPGA processors without requiring actual execution on target processor or ISS. Experimental results show that this technique estimates performance of a widely-used FPGA processor with an average error of 2% in the order of seconds.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085116\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085116","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Compiler-assisted technique for rapid performance estimation of FPGA-based processors
This paper proposes a compiler-assisted technique to rapidly estimate performance of a wide range of FPGA processors without requiring actual execution on target processor or ISS. Experimental results show that this technique estimates performance of a widely-used FPGA processor with an average error of 2% in the order of seconds.