“Manufacturing test of systems-on-a-chip (SoCs)”

Abstract

Testing chips after manufacture, unlike producing transistors on a chip, does not enjoy the scaling offered by Moore's law. This tutorial will outline the increasing difficulties with manufacturing test and discuss approaches to manage the complexity of testing SoCs, including generation and design-for-test techniques for classic “stuck-at” faults as well as small delay defects which are becoming more common in scaled technologies. Issues with testing embedded analog, mixed-signal and RF modules will be addressed. Test approaches which use the computational resources within a (SoC) to test itself will also be discussed. The embedded processor in the SoC can test itself by running instruction sequences from memory. The processor can be used to test other cores in the SoC, including mixed-signal cores for analog and RF specifications, with the help of design-for-test structures such as on-chip sensors.