{"title":"一种基于工艺变化下小信号模型的模拟电路性能影响估计方法","authors":"Po-Yu Kuo, Siwat Saibua, Dian Zhou","doi":"10.1109/SOCC.2011.6085098","DOIUrl":null,"url":null,"abstract":"Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number of simulation runs. This paper proposes a novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. The accuracy of the small signal model has been verified with CMOS circuit. The proposed approach has been demonstrated by a CMOS two-stage operational transconductance amplifier (OTA). To achieve an accurate estimate, the modified small signal model which consider more parasitic capacitors in CMOS transistor, has been applied in the proposed approach. By applying the proposed approach based on optimization method, the upper and lower bounds of magnitude and phase, can be evaluated accurately in much less computation time compared to Monte Carlo simulations. All experimental results are carried out using a standard 0.35-µm CMOS process technology.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations\",\"authors\":\"Po-Yu Kuo, Siwat Saibua, Dian Zhou\",\"doi\":\"10.1109/SOCC.2011.6085098\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number of simulation runs. This paper proposes a novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. The accuracy of the small signal model has been verified with CMOS circuit. The proposed approach has been demonstrated by a CMOS two-stage operational transconductance amplifier (OTA). To achieve an accurate estimate, the modified small signal model which consider more parasitic capacitors in CMOS transistor, has been applied in the proposed approach. By applying the proposed approach based on optimization method, the upper and lower bounds of magnitude and phase, can be evaluated accurately in much less computation time compared to Monte Carlo simulations. All experimental results are carried out using a standard 0.35-µm CMOS process technology.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085098\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations
Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number of simulation runs. This paper proposes a novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. The accuracy of the small signal model has been verified with CMOS circuit. The proposed approach has been demonstrated by a CMOS two-stage operational transconductance amplifier (OTA). To achieve an accurate estimate, the modified small signal model which consider more parasitic capacitors in CMOS transistor, has been applied in the proposed approach. By applying the proposed approach based on optimization method, the upper and lower bounds of magnitude and phase, can be evaluated accurately in much less computation time compared to Monte Carlo simulations. All experimental results are carried out using a standard 0.35-µm CMOS process technology.