A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuit

Abstract

A clock skew-compensation and/or duty-cycle-correction circuit (CSADC) is indispensably required to maximize the performance of a synchronous double edge clocking system. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more design complexity. A compact delay-recycled CSADC is proposed in this work. Compared to conventional CSADCs, the proposed circuit achieves at least a 2.5 times reduction in lock-in cycles, a 5.49 times reduction in power, and a 3.67 times reduction in power bandwidth ratio.