{"title":"一个多段时钟方案,以减少片上电磁干扰","authors":"B. Mesgarzadeh, I. Zadeh, A. Alvandpour","doi":"10.1109/SOCC.2011.6085110","DOIUrl":null,"url":null,"abstract":"This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A multi-segment clocking scheme to reduce on-chip EMI\",\"authors\":\"B. Mesgarzadeh, I. Zadeh, A. Alvandpour\",\"doi\":\"10.1109/SOCC.2011.6085110\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085110\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085110","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multi-segment clocking scheme to reduce on-chip EMI
This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.