{"title":"现代乱序处理器的低功耗三态寄存器文件设计","authors":"Na Gong, Geng Tang, Jinhui Wang, R. Sridhar","doi":"10.1109/SOCC.2011.6085113","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a novel integrated circuit and architectural level technique to reduce power consumption of register files in high-performance microprocessors. Our simulation results on 32-nm process show 12.7–14.1% power reduction for ROB (Reorder Buffer)-based microprocessors and 12.4–17.9% power reduction for checkpoint-based microprocessors, respectively, with less than 5% impact on excess time.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low power tri-state register files design for modern out-of-order processors\",\"authors\":\"Na Gong, Geng Tang, Jinhui Wang, R. Sridhar\",\"doi\":\"10.1109/SOCC.2011.6085113\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a novel integrated circuit and architectural level technique to reduce power consumption of register files in high-performance microprocessors. Our simulation results on 32-nm process show 12.7–14.1% power reduction for ROB (Reorder Buffer)-based microprocessors and 12.4–17.9% power reduction for checkpoint-based microprocessors, respectively, with less than 5% impact on excess time.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085113\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085113","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low power tri-state register files design for modern out-of-order processors
In this paper, we propose a novel integrated circuit and architectural level technique to reduce power consumption of register files in high-performance microprocessors. Our simulation results on 32-nm process show 12.7–14.1% power reduction for ROB (Reorder Buffer)-based microprocessors and 12.4–17.9% power reduction for checkpoint-based microprocessors, respectively, with less than 5% impact on excess time.