平面规划在早期芯片规划中的挑战

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI:10.1109/SOCC.2011.6085096

Jeonghee Shin, J. Darringer, Guojie Luo, M. Aharoni, Alexey Lvov, Gi-Joon Nam, Michael B. Healy

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引用次数: 5

摘要

早期的芯片规划变得越来越重要，因为服务器系统设计人员努力探索一个更大的设计空间，在先进的硅技术中使用多个核心和加速器，包括3D芯片堆叠。在早期的芯片规划中，设计人员寻找最能满足无数约束和目标的高级设计和布局。在本文中，我们讨论了在早期阶段应用传统平面规划工具的经验，并提出了如何将其用于早期平面规划的建议。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Floorplanning challenges in early chip planning

Early chip planning is becoming more critical as server system designers strive to explore a large design space with multiple cores and accelerators in an advanced silicon technology that includes 3D chip stacking. During early chip planning, designers search for the high-level design and layout that best satisfies a myriad of constraints and targets. In this paper, we discuss our experience in applying traditional floorplanning tools at this early stage and suggest how they might be adapted for early floorplanning.

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2011 IEEE International SOC Conference

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