A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system

Abstract

The current mode digital-to-analog converter (iDAC) has been widely used in finite-impulse response (FIR) filter implementations as it is well-suited for high-speed operation. This paper proposes a novel solution to reduce the signal feed-through problem commonly encountered in current mode digital-to-analog converters in pre-emphasis circuits. To improve the eye opening, the circuit must be able to limit the flow of feed-through signal to the summing node. The proposed multi-tap pre-emphasis circuit has been simulated using an IBM 130nm CMOS technology.