{"title":"Well tapping methodologies in power-gating design","authors":"K. Shi, D. Tester","doi":"10.1109/SOCC.2011.6085133","DOIUrl":null,"url":null,"abstract":"65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production power-gating designs considering design schedule, leakage power, chip area and complexity.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085133","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production power-gating designs considering design schedule, leakage power, chip area and complexity.