电源门控设计中的攻丝方法

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI:10.1109/SOCC.2011.6085133

K. Shi, D. Tester

{"title":"电源门控设计中的攻丝方法","authors":"K. Shi, D. Tester","doi":"10.1109/SOCC.2011.6085133","DOIUrl":null,"url":null,"abstract":"65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production power-gating designs considering design schedule, leakage power, chip area and complexity.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Well tapping methodologies in power-gating design\",\"authors\":\"K. Shi, D. Tester\",\"doi\":\"10.1109/SOCC.2011.6085133\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production power-gating designs considering design schedule, leakage power, chip area and complexity.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085133\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085133","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

65nm及以上的CMOS设计通常采用“无带”文库单元，不提供内置n孔或衬底接头，从而提高了单元密度。这种电池效率导致功率门控设计的额外布局复杂性。在考虑设计进度、漏功率、芯片面积和复杂度的情况下，介绍了生产电源门控设计的三种攻井方法。

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Well tapping methodologies in power-gating design

65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production power-gating designs considering design schedule, leakage power, chip area and complexity.

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2011 IEEE International SOC Conference

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