Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits

Abstract

This paper proposes a synthesis methodology for constructing Application-Specific NoCs topology in 3D chips. The multi-cores and communications can be synthesized simultaneously in the system-level floorplanning process with fault tolerant consideration. As a result, the experimental results show that the proposed approach produces 3D NoCs with lower power dissipation than previous works in multimedia applications with relatively small overhead of the number of Through-Silicon-Vias (TSVs) for achieving 100% fault tolerance in 3D NoC links based on single fault assumption.