采用通孔可配置晶体管阵列规则布局结构设计复杂电路

2011 IEEE International SOC Conference Pub Date : 2011-11-21 DOI:10.1109/SOCC.2011.6085126

M. Pons, F. Moll, A. Rubio, J. Abella, X. Vera, Antonio González

{"title":"采用通孔可配置晶体管阵列规则布局结构设计复杂电路","authors":"M. Pons, F. Moll, A. Rubio, J. Abella, X. Vera, Antonio González","doi":"10.1109/SOCC.2011.6085126","DOIUrl":null,"url":null,"abstract":"Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of complex circuits using the Via-Configurable transistor array regular layout fabric\",\"authors\":\"M. Pons, F. Moll, A. Rubio, J. Abella, X. Vera, Antonio González\",\"doi\":\"10.1109/SOCC.2011.6085126\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085126\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085126","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

布局规则将是未来CMOS技术的强制性要求，以减轻可制造性问题。然而，现有的CAD工具不能满足规则约束的要求。本文提出了一种新的通过可配置晶体管阵列生成规则布局的方法，重点是减少与规则相关的面积开销。在45nm技术节点上的ISCAS85基准测试结果表明，可以获得与标准电池方法相当的区域。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design of complex circuits using the Via-Configurable transistor array regular layout fabric

Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2011 IEEE International SOC Conference

自引率

0.00%

发文量