{"title":"Novel adaptive keeper LBL technique for low power and high performance register files","authors":"Na Gong, Geng Tang, Jinhui Wang, R. Sridhar","doi":"10.1109/SOCC.2011.6085071","DOIUrl":null,"url":null,"abstract":"This paper develops a novel adaptive keeper local bit line (LBL) technique to achieve low power and high performance register files design. To avoid increasing the implementation hardware overhead, the proposed technique employs a clock-combined unit to generate the body voltage of keeper. We evaluate the effectiveness of the proposed technique in a two-cycle 64-entries×32b register file design for 8GHz operation in 1V, 32nm high-K Metal-Gate technology. HSPICE simulation results show that the delay time is reduced by 29% and the power consumption is reduced by 36.1%–46.2% depending on the number of reading ports, as compared to the tradition register files design. Moreover, the proposed technique shows good robustness to noise and process variations.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085071","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper develops a novel adaptive keeper local bit line (LBL) technique to achieve low power and high performance register files design. To avoid increasing the implementation hardware overhead, the proposed technique employs a clock-combined unit to generate the body voltage of keeper. We evaluate the effectiveness of the proposed technique in a two-cycle 64-entries×32b register file design for 8GHz operation in 1V, 32nm high-K Metal-Gate technology. HSPICE simulation results show that the delay time is reduced by 29% and the power consumption is reduced by 36.1%–46.2% depending on the number of reading ports, as compared to the tradition register files design. Moreover, the proposed technique shows good robustness to noise and process variations.