A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode

Yan Zhao, N. Tan, Kun-Ming Yang, Shupeng Zhong, Changyou Men
{"title":"A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode","authors":"Yan Zhao, N. Tan, Kun-Ming Yang, Shupeng Zhong, Changyou Men","doi":"10.1109/SOCC.2011.6085091","DOIUrl":null,"url":null,"abstract":"A single-phase energy metering SoC in TSMC 0.25um mixed-mode embedded FLASH technology is designed. While integrating four channel sigma-delta ADCs, PLL, oscillation circuit, regulators, temperature sensor, 8-bit CPU core, 32K byte FLASH memory, 1K byte SRAM memory, energy metering engine, and various on-chip peripherals, a small die size is achieved due to the implement of an 32-bit fixed-point Instruction and Architecture Specific DSP (IAS-DSP) to conduct the carefully designed multi-rate energy metering algorithm. To satisfy critical power restrictive applications, several ultra low power metering modes are designed. With these modes and the IAS-DSP, there is only about 100uA current dissipation while metering accuracy still meets industrial standards. The experimental results also prove excellent EMI rejection features. The chip is currently in production and millions has been shipped.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

A single-phase energy metering SoC in TSMC 0.25um mixed-mode embedded FLASH technology is designed. While integrating four channel sigma-delta ADCs, PLL, oscillation circuit, regulators, temperature sensor, 8-bit CPU core, 32K byte FLASH memory, 1K byte SRAM memory, energy metering engine, and various on-chip peripherals, a small die size is achieved due to the implement of an 32-bit fixed-point Instruction and Architecture Specific DSP (IAS-DSP) to conduct the carefully designed multi-rate energy metering algorithm. To satisfy critical power restrictive applications, several ultra low power metering modes are designed. With these modes and the IAS-DSP, there is only about 100uA current dissipation while metering accuracy still meets industrial standards. The experimental results also prove excellent EMI rejection features. The chip is currently in production and millions has been shipped.
具有IAS-DSP和超低功耗计量模式的单相电能计量SoC
设计了一种采用台积电0.25um混合模式嵌入式FLASH技术的单相电能计量SoC。集成了四通道sigma-delta adc、锁相环、振荡电路、稳压电路、温度传感器、8位CPU核心、32K字节FLASH存储器、1K字节SRAM存储器、能量计量引擎和各种片上外设,由于采用了32位定点指令与架构专用DSP (IAS-DSP)来执行精心设计的多速率能量计量算法,因此实现了小芯片尺寸。为了满足关键功率限制应用,设计了几种超低功率计量模式。使用这些模式和IAS-DSP,只有大约100uA的电流损耗,同时计量精度仍然符合工业标准。实验结果也证明了该系统具有良好的电磁干扰抑制特性。该芯片目前正在生产中,已经出货了数百万台。
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