Yan Zhao, N. Tan, Kun-Ming Yang, Shupeng Zhong, Changyou Men
{"title":"具有IAS-DSP和超低功耗计量模式的单相电能计量SoC","authors":"Yan Zhao, N. Tan, Kun-Ming Yang, Shupeng Zhong, Changyou Men","doi":"10.1109/SOCC.2011.6085091","DOIUrl":null,"url":null,"abstract":"A single-phase energy metering SoC in TSMC 0.25um mixed-mode embedded FLASH technology is designed. While integrating four channel sigma-delta ADCs, PLL, oscillation circuit, regulators, temperature sensor, 8-bit CPU core, 32K byte FLASH memory, 1K byte SRAM memory, energy metering engine, and various on-chip peripherals, a small die size is achieved due to the implement of an 32-bit fixed-point Instruction and Architecture Specific DSP (IAS-DSP) to conduct the carefully designed multi-rate energy metering algorithm. To satisfy critical power restrictive applications, several ultra low power metering modes are designed. With these modes and the IAS-DSP, there is only about 100uA current dissipation while metering accuracy still meets industrial standards. The experimental results also prove excellent EMI rejection features. The chip is currently in production and millions has been shipped.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode\",\"authors\":\"Yan Zhao, N. Tan, Kun-Ming Yang, Shupeng Zhong, Changyou Men\",\"doi\":\"10.1109/SOCC.2011.6085091\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-phase energy metering SoC in TSMC 0.25um mixed-mode embedded FLASH technology is designed. While integrating four channel sigma-delta ADCs, PLL, oscillation circuit, regulators, temperature sensor, 8-bit CPU core, 32K byte FLASH memory, 1K byte SRAM memory, energy metering engine, and various on-chip peripherals, a small die size is achieved due to the implement of an 32-bit fixed-point Instruction and Architecture Specific DSP (IAS-DSP) to conduct the carefully designed multi-rate energy metering algorithm. To satisfy critical power restrictive applications, several ultra low power metering modes are designed. With these modes and the IAS-DSP, there is only about 100uA current dissipation while metering accuracy still meets industrial standards. The experimental results also prove excellent EMI rejection features. The chip is currently in production and millions has been shipped.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085091\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode
A single-phase energy metering SoC in TSMC 0.25um mixed-mode embedded FLASH technology is designed. While integrating four channel sigma-delta ADCs, PLL, oscillation circuit, regulators, temperature sensor, 8-bit CPU core, 32K byte FLASH memory, 1K byte SRAM memory, energy metering engine, and various on-chip peripherals, a small die size is achieved due to the implement of an 32-bit fixed-point Instruction and Architecture Specific DSP (IAS-DSP) to conduct the carefully designed multi-rate energy metering algorithm. To satisfy critical power restrictive applications, several ultra low power metering modes are designed. With these modes and the IAS-DSP, there is only about 100uA current dissipation while metering accuracy still meets industrial standards. The experimental results also prove excellent EMI rejection features. The chip is currently in production and millions has been shipped.