A CAD methodology for automatic topology selection & sizing

Abstract

Over the years, as system on chip is increasingly incorporating analog functionalities, there is a need of a tool, which can automate the analog topology selection and sizing flow. We develop one efficient methodology to automatically select the best topology given only the user specifications. The proposed topology selection is a multilevel screening process inherited from geometric programming (GP) by sequentially introducing sub-sets of requirements. This helps to prune out unfit topologies at early stage and hence not costing much computational effort. Use of GP ensures fast convergence with optimal solution. Apart from the speed advantage, compared to the existing literature, methodology has better representation of topology performance expressions. We propose to use two levels of performance expressions. First one is technology independent and the second one is technology specific. This bifurcation of performance expressions help in quick technology migration. Third contribution is automatic node expression generation which are required for dc performance evaluation. The proposed methodology is used for selecting optimal error amplifier topology for low dropout regulator (LDO).