A gate sizing method for glitch power reduction

Abstract

Due to the difficulty in estimating dynamic power at the gate level, a quantity called power metric and its efficient calculation method are introduced in this work. Based on the proposed power metric, a heuristic gate sizing algorithm for glitch power reduction is proposed for semi-custom design. The proposed heuristic algorithm minimizes the total power metric of a circuit. According to the experimental results on 8 ISCAS85 benchmark circuits and 5 real industrial circuits, more than 30% average glitch power reduction and 15.5% average total power reduction can be achieved by means of the proposed algorithm, respectively. The achieved improvements on power and area both are more than those by means of conventional gate sizing algorithms.