PVT variations aware optimal sleep vector determination of dual VT domino OR circuits

Abstract

In this paper, determining optimal leakage vector for dual Vt domino OR circuits is explored under process, supply voltage, and temperature (PVT) variations based on 65 nm bulk and 45 nm high k/metal gate (HK+MG) technologies, while considering design parameters, environmental parameters, working characteristics of circuits, and application cases. It concludes that the high clock signal with high inputs (CHIH) vector is the optimal sleep vector for practical low leakage register files applications, and the HK+MG technology further highlights the effectiveness of the CHIH vector as compared to other vectors.