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1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon最新文献

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Test strategy sensitivity to floating gate fault parameter 测试策略对浮栅故障参数的敏感性
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630259
M. Renovell, Y. Bertrand, F. Azais
{"title":"Test strategy sensitivity to floating gate fault parameter","authors":"M. Renovell, Y. Bertrand, F. Azais","doi":"10.1109/ICISS.1997.630259","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630259","url":null,"abstract":"This paper studies the detectability of floating gate faults considering static voltage, dynamic voltage and static current strategies. It is shown that the behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters (polysilicon-to-bulk capacitance). It is shown that a floating gate fault can induce abnormal logic values, additional delays or increased static current (I/sub DDQ/). Consequently, any test strategy is able to detect floating gate faults, each one for a given range of the unpredictable parameter. It is then demonstrated that the fundamental criterion for test strategy efficiency evaluation is the consideration of the corresponding intervals.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133973148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A parallel DSP testbed with a heterogeneous and reconfigurable network fabric 一种具有异构和可重构网络结构的并行DSP试验台
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630274
S. Tewksbury, K. Devabattini, V. Gandikota
{"title":"A parallel DSP testbed with a heterogeneous and reconfigurable network fabric","authors":"S. Tewksbury, K. Devabattini, V. Gandikota","doi":"10.1109/ICISS.1997.630274","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630274","url":null,"abstract":"A testbed for investigation of heterogeneous and reconfigurable data network fabrics supporting a parallel DSP computational accelerator is described. The DSP processors are large-grained processors (Analog Devices SHARC DSPs), with a variety of parallel DSP array architectures possible. The network fabric is intended to be reconfigurable (within a rich but necessarily limited set of structures) to adapt to the needs of a sequence of image processing algorithms being executed (e.g., in a medical image processing environment). The testbed will exploit conventional FPGA components to provide reconfigurable network structures and will exploit commercial high-speed interconnect components emerging for applications such as board-to-board applications. As a computational accelerator, the testbed is intended to be controlled by a host processor, with the host processor cooperating in the definition of the changes in the structure of the network structure as execution of a sequence of image processing algorithms proceeds.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131332647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Electrical modeling and simulation for mixed-signal interconnect and packaging 混合信号互连和封装的电气建模和仿真
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630249
A. Cangellaris
{"title":"Electrical modeling and simulation for mixed-signal interconnect and packaging","authors":"A. Cangellaris","doi":"10.1109/ICISS.1997.630249","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630249","url":null,"abstract":"The explosive growth of wireless communications, combined with the rapid advances in high-performance portable computing, are driving the microelectronics industry toward the development of a variety of multi-functional, low-cost, compact, mixed-signal electronic products. These new products call for novel, often revolutionary, practices in functional block integration and packaging. Some of the challenges associated with the electrical design and rapid prototyping of these systems are discussed in this paper. Examples are given of existing electromagnetic modeling methodologies and associated CAD tools that can be used today to facilitate the design of these novel packages. The paper concludes with a brief discussion of on-going research activities toward the enhancement of these modeling/simulation methodologies and the eventual establishment of an electromagnetic CAD environment for mixed-signal system electrical design.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133037048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The microprocessor is no longer general purpose: why future reconfigurable platforms will win 微处理器不再是通用的:为什么未来的可重构平台会赢
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630241
R. Hartenstein
{"title":"The microprocessor is no longer general purpose: why future reconfigurable platforms will win","authors":"R. Hartenstein","doi":"10.1109/ICISS.1997.630241","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630241","url":null,"abstract":"The paper is a proposal for a radical methodological change in R&D of dynamically reconfigurable circuits. The paper illustrates, that the current main stream approach based on placement and routing is not very likely to obtain the area-efficiency and throughput needed to cope with the emerging crisis cost of future silicon technology generations. The proposed changes include both: architectural principles and fundamental issues in application development support environments. The paper illustrates the feasibility of general purpose programmable accelerators and their commercialization. The paper highlights computer systems' increasing dependency on add-on accelerators. It shows, why only by a new methodology reconfigurable hardware will overcome its role as a niche technology and become competitive to ASICs and other hardwired accelerators. It illustrates the possible coming crisis of ASIC design based on wasting chip area by placement and routing and discusses the vision of software-only implementation of accelerators.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129053923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Enhancement of MCM testability using an embedded reconfigurable FPGA 使用嵌入式可重构FPGA增强MCM可测试性
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630257
J. York, T. Powell, P. Dehkordi, D. Bouldin
{"title":"Enhancement of MCM testability using an embedded reconfigurable FPGA","authors":"J. York, T. Powell, P. Dehkordi, D. Bouldin","doi":"10.1109/ICISS.1997.630257","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630257","url":null,"abstract":"The testability of an MCM can be enhanced significantly for very little cost whenever a reprogrammable FPGA component that is already embedded in the MCM for functionality is utilized for diagnostics. This approach can have some of the characteristics of a smart substrate which uses the scan cell beside-the-signal-path (BSP) methodology. The design and implementation of an MCM with this capability is presented along with descriptions of the self-test algorithms, fault isolation and real-time testing and monitoring that this method provides.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130800942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
K-way partitioning under timing, pin, and area constraints 在时序、引脚和面积约束下的k路划分
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630250
G. Tumbush, D. Bhatia
{"title":"K-way partitioning under timing, pin, and area constraints","authors":"G. Tumbush, D. Bhatia","doi":"10.1109/ICISS.1997.630250","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630250","url":null,"abstract":"Circuit partitioning is a very extensively studied problem. Our proposed methodology easily extends to multiple constraints that are very dominant in the design of large scale VLSI systems. In this paper we formulate the problem as a nonlinear program (NLP). The NLP is solved for the objective of minimum cutset size under the constraints of pins, area, and timing. We have tested the unified framework for area, timing, and pin constraints. The NLP is solved using the commercial LP/NLP solver MINOS. We have done extensive testing using large scale RT level benchmarks and have shown that our methods can be used for exploring the design space for obtaining constraint satisfying system designs. We also provide extensions for solving system design problems where a choice between multiple technologies, packaging components, performance, cost, yield, and more can be the constraints for design related decisions.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130666898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Economics modeling of multichip systems testing strategies 多芯片系统测试策略的经济学建模
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630278
M. Abadir
{"title":"Economics modeling of multichip systems testing strategies","authors":"M. Abadir","doi":"10.1109/ICISS.1997.630278","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630278","url":null,"abstract":"Summary form only given, as follows. To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply Design For Test (DFT) and Built-in Self Test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental trade-off analysis data generated for some leading-edge multichip designs are also presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10-20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s).","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127503941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DSP architectures, algorithms, and code-generation: fission or fusion? DSP架构、算法和代码生成:裂变还是融合?
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630264
R. Simar
{"title":"DSP architectures, algorithms, and code-generation: fission or fusion?","authors":"R. Simar","doi":"10.1109/ICISS.1997.630264","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630264","url":null,"abstract":"Continuing dramatic improvements in semiconductor manufacturing processes are enabling radical new signal-processing architectures at the chip level. The development of these new architectures must be coupled, a fusion, with clearly defined target applications, a thorough analysis of applicable signal processing algorithms, and significant advancements in code-generation technology. The TMS320C6x development program involved the codevelopment of the VelociTI architecture, a new code-generation environment, and a large set of representative benchmarks.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122545656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A dual mode IEEE multiplier 双模IEEE乘法器
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630271
G. Even, S. Mueller, P. Seidel
{"title":"A dual mode IEEE multiplier","authors":"G. Even, S. Mueller, P. Seidel","doi":"10.1109/ICISS.1997.630271","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630271","url":null,"abstract":"We present an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the latency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fifteen logic levels. A single-precision multiplication can be followed immediately by another multiplication of either single or double-precision, A double-precision multiplication requires one stall cycle, namely, two cycles after issuing a double-precision multiplication, a new multiplication of either precision can be issued. Therefore, the throughput in single-precision is one multiplication per clock cycle, and the throughput in double-precision is one multiplication per two clock cycles. Hardware cost is reduced by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126361535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A low-latency serial architecture for the 1-D discrete wavelet transform 一维离散小波变换的低延迟串行结构
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630273
L. Breveglieri, V. Piuri, M. Rona, E. Swartzlander
{"title":"A low-latency serial architecture for the 1-D discrete wavelet transform","authors":"L. Breveglieri, V. Piuri, M. Rona, E. Swartzlander","doi":"10.1109/ICISS.1997.630273","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630273","url":null,"abstract":"The 1-Dimensional Discrete Wavelet Transform is a powerful DSP technique for several application areas. Dedicated VLSI processors are often required by real-time applications due to the high amount of arithmetic operations; the circuit complexity is usually a relevant constraint for several low-cost applications as well as for complex systems having strong dimensional limits on the implementation (e.g., in aerospace applications). This paper presents the architectural design of a low-latency bit-serial 1-Dimensional Wavelet Transform Processor.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130315832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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