发布求助
文献互助 智能选刊 最新文献

1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon最新文献

筛选
英文 中文
System-level power evaluation metrics 系统级功率评估指标
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630275
W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano
{"title":"System-level power evaluation metrics","authors":"W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano","doi":"10.1109/ICISS.1997.630275","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630275","url":null,"abstract":"High-level power estimation is a key issue for IC designers and system engineers. The goal is to widely explore the architectural design space and to compare alternative solutions, while maintaining an acceptable accuracy and a competitive design time. In this paper, an approach is proposed for evaluating the system-level power consumption of embedded systems implemented by using VLSI circuits. Accurate and efficient early power evaluation metrics have been defined to guide the system-level partitioning phase of a more general HW/SW co-design approach for control dominated embedded systems. The hardware and software contributions to the power consumption at the system-level have been considered as well as the contribution of the HW/SW communication.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134583841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Possibilities and limitations of I/sub DDQ/ testing in submicron CMOS 在亚微米CMOS中I/sub DDQ/测试的可能性和局限性
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630258
Joan Figueras
{"title":"Possibilities and limitations of I/sub DDQ/ testing in submicron CMOS","authors":"Joan Figueras","doi":"10.1109/ICISS.1997.630258","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630258","url":null,"abstract":"I/sub DDQ/ testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which scope other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114138170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
High speed lensless integrated proximity sensor 高速无透镜集成接近传感器
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630253
G. Chapman, D. E. Bergen
{"title":"High speed lensless integrated proximity sensor","authors":"G. Chapman, D. E. Bergen","doi":"10.1109/ICISS.1997.630253","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630253","url":null,"abstract":"An integrated sensor array has been developed using lensless techniques that produces a high accuracy proximity measurement from contact to 18 mm. An integrated optical detector and processing circuitry chip was developed for this application. It locates the brightest spot within an optical array which will output the proximity position every 5.3 /spl mu/s.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115278195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Clock cycle estimations for future microprocessor generations 未来微处理器世代的时钟周期估计
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630247
P. D. Fischer
{"title":"Clock cycle estimations for future microprocessor generations","authors":"P. D. Fischer","doi":"10.1109/ICISS.1997.630247","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630247","url":null,"abstract":"In the past 50 years, the semiconductor industry has experienced unprecedented growth. Identifying pivotal factors and technology trends in future generations will be key to understanding how we can maintain the historical growth and improve customer value. Processor performance will be one of the essential factors in this quest. This paper presents a high-level model of microprocessor clock-cycle performance. The model considers the impact of interconnect technology, device and circuit technology, along with architectural and physical design factors, to estimate clock speeds of future microprocessors.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123618152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The application of reconfigurable processors to MEMS calibration and signal processing in inertial navigation systems 可重构处理器在惯性导航系统中MEMS标定与信号处理中的应用
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630254
J. Arrigo, K. Page, P. Chau, N. Tien
{"title":"The application of reconfigurable processors to MEMS calibration and signal processing in inertial navigation systems","authors":"J. Arrigo, K. Page, P. Chau, N. Tien","doi":"10.1109/ICISS.1997.630254","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630254","url":null,"abstract":"Advances in MEMS (micromechanical systems) and integrated circuits have made it feasible to further miniaturize smart sensor technology for inertial navigation systems. An element of smart sensor technology of particular interest is the use of reconfigurable logic, which is a method that can be employed to minimize the hardware needed to perform a variety of tasks concerned with sensor data reduction. Especially during subsystem development, using reconfigurable hardware facilitates rapid assessment and selection of different sensor instrumentation methods. Coordinate transformations and other computations involved in inertial navigation and GPS (global positioning system) data integration that can be performed with reconfigurable logic are described below. INS (inertial navigational system) and GPS readings are needed for future advances in terrestrial vehicle applications like geolocation and automatic target recognition. Preliminary experimental MEMS structures that are expected to be incorporated into accelerometer and other subsystem designs are also described below.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126882607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient controller design for telescopic units 伸缩装置的高效控制器设计
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630272
L. Benini, E. Macii, M. Poncino
{"title":"Efficient controller design for telescopic units","authors":"L. Benini, E. Macii, M. Poncino","doi":"10.1109/ICISS.1997.630272","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630272","url":null,"abstract":"Telescopic units represent an effective and innovative design option for increasing the average throughput of a combinational block. Throughput improvement is obtained at the price of a small reduction in average latency by allowing the unit to run with variable latency. Although this design paradigm has proved to be very effective, there are still some issues that need to be addressed before it can be used in practice: First, the introduction of variable-latency units complicates the control flow, and therefore the design of the controller. Second, the availability of telescopic units affects the way the high-level synthesis algorithms operate; this is because such units provide additional alternatives for realizing maximum-speed designs. This paper focuses on the first aspect, and gives a general criterion for the re-design of a controller when some data-path units are replaced by telescopic units. The viability of the proposed approach is demonstrated through a case study.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"357 1419 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Architecture of a multiprocessor system with embedded DRAM for large area integration 用于大面积集成的嵌入式DRAM多处理器系统的体系结构
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630270
K. Herrmann, J. Hilgenstock, P. Pirsch
{"title":"Architecture of a multiprocessor system with embedded DRAM for large area integration","authors":"K. Herrmann, J. Hilgenstock, P. Pirsch","doi":"10.1109/ICISS.1997.630270","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630270","url":null,"abstract":"The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the processors. The processors perform the complete set of coding or decoding tasks on the assigned portion of the image. Because each processor is equipped with sufficient memory for image storage and processing power, no additional external hardware is required. The architecture of each processor and embedded DRAM is designed for large area integration. This allows the implementation of a complex video coding system on a single chip.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"937 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123065953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A reconfigurable Markov chain simulator for analysis of parallel systems 用于并行系统分析的可重构马尔可夫链模拟器
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630251
O. Yamamoto, K. Shibata, H. Kurosawa, H. Amano
{"title":"A reconfigurable Markov chain simulator for analysis of parallel systems","authors":"O. Yamamoto, K. Shibata, H. Kurosawa, H. Amano","doi":"10.1109/ICISS.1997.630251","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630251","url":null,"abstract":"Markov chain is a convenient tool to analyze parallel systems for architects who are not experts of theoretical analysis. However, it is sometimes difficult to use especially when the model becomes complicated or extremely small probabilities are used in the model. In this paper, we propose a reconfigurable Markov chain simulation system and evaluate on a reconfigurable testbed. In this system, a user describes the target system in a dedicated description language called \"Taico\". The description is automatically translated into the Verilog-HDL description, of the Markov chain simulator. Then, the simulator is implemented on a reconfigurable testbed called FLEMING, and executed directly. From the evaluation with analysis of example parallel systems, it appears that the simulation speed of proposed system is more than hundreds times faster than software simulation on a high speed workstation.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128600518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
How to lay out arrays spared by rows and columns 如何布局阵列的行和列
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630244
L. LaForge
{"title":"How to lay out arrays spared by rows and columns","authors":"L. LaForge","doi":"10.1109/ICISS.1997.630244","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630244","url":null,"abstract":"Perhaps the most common fault tolerant architecture configures a nominal t/spl times/at array using bt dedicated spare rows and ct dedicated spare columns. We counterexample an outstanding conjecture by constructively showing how dedicated sparing can be laid out in area proportional to the number of elements. However, we find that dedicated sparing is more costly than homogeneous extraction of a t/spl times/at array from a (1+b)t/spl times/(a+c)t array. i) In the presence of failures whose distribution is worst-case, iid, or clustered, the fault tolerance of either architecture is /spl Theta/(t/sup -1/). ii) At constant proportion of failures, the area of homogeneous arrays is /spl Theta/(exp t), while that of dedicated sparing is /spl Omega/(exp t). iii) The worst-case wirelength of either architecture is /spl Theta/(ct). iv) The best-case wirelength /spl Theta/(1) of homogeneous sparing is less than that /spl Theta/(t) of dedicated sparing. V) Probabilisticaily, homogeneous sparing has O(log t) wirelength, less than that /spl Theta/(t) of dedicated sparing. For large t, moreover, row-column sparing is more costly than local sparing.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115434178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A scalar cost function for analyzing the quality of totally self-checking design methodologies 一种用于分析全自检设计方法质量的标量代价函数
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630260
C. Bolchini, F. Salice, D. Sciuto
{"title":"A scalar cost function for analyzing the quality of totally self-checking design methodologies","authors":"C. Bolchini, F. Salice, D. Sciuto","doi":"10.1109/ICISS.1997.630260","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630260","url":null,"abstract":"This paper proposes a scalar cost function for analyzing the quality of Totally Self-Checking combinational devices; in particular the presented evaluator allows one to take into account other significant aspects affecting a TSC implementation rather than area overhead. The cost function is based on a measure which dynamically defines the probability to achieve the TSC goal at cycle t with respect to fault occurrence and circuit stimulation. As some experimental results highlight, the smallest circuits aren't always the most desirable one.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116254788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信