用于大面积集成的嵌入式DRAM多处理器系统的体系结构

1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI:10.1109/ICISS.1997.630270

K. Herrmann, J. Hilgenstock, P. Pirsch

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引用次数: 0

摘要

提出了一种基于mimd的多处理器视频编码系统的体系结构。它由许多相同的总线连接处理器组成，每个处理器都专门适应视频编码算法，并配备嵌入式DRAM用于存储图像数据。每个待处理的图像被静态分割成矩形场，分布在处理器之间。处理器对所述图像的指定部分执行完整的编码或解码任务集。因为每个处理器都配备了足够的内存用于图像存储和处理能力，所以不需要额外的外部硬件。每个处理器和嵌入式DRAM的架构都是为大面积集成而设计的。这允许在单个芯片上实现复杂的视频编码系统。

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Architecture of a multiprocessor system with embedded DRAM for large area integration

The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the processors. The processors perform the complete set of coding or decoding tasks on the assigned portion of the image. Because each processor is equipped with sufficient memory for image storage and processing power, no additional external hardware is required. The architecture of each processor and embedded DRAM is designed for large area integration. This allows the implementation of a complex video coding system on a single chip.

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1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon

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