System-level power evaluation metrics

Abstract

High-level power estimation is a key issue for IC designers and system engineers. The goal is to widely explore the architectural design space and to compare alternative solutions, while maintaining an acceptable accuracy and a competitive design time. In this paper, an approach is proposed for evaluating the system-level power consumption of embedded systems implemented by using VLSI circuits. Accurate and efficient early power evaluation metrics have been defined to guide the system-level partitioning phase of a more general HW/SW co-design approach for control dominated embedded systems. The hardware and software contributions to the power consumption at the system-level have been considered as well as the contribution of the HW/SW communication.