L. Breveglieri, V. Piuri, M. Rona, E. Swartzlander
{"title":"A low-latency serial architecture for the 1-D discrete wavelet transform","authors":"L. Breveglieri, V. Piuri, M. Rona, E. Swartzlander","doi":"10.1109/ICISS.1997.630273","DOIUrl":null,"url":null,"abstract":"The 1-Dimensional Discrete Wavelet Transform is a powerful DSP technique for several application areas. Dedicated VLSI processors are often required by real-time applications due to the high amount of arithmetic operations; the circuit complexity is usually a relevant constraint for several low-cost applications as well as for complex systems having strong dimensional limits on the implementation (e.g., in aerospace applications). This paper presents the architectural design of a low-latency bit-serial 1-Dimensional Wavelet Transform Processor.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"232 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICISS.1997.630273","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The 1-Dimensional Discrete Wavelet Transform is a powerful DSP technique for several application areas. Dedicated VLSI processors are often required by real-time applications due to the high amount of arithmetic operations; the circuit complexity is usually a relevant constraint for several low-cost applications as well as for complex systems having strong dimensional limits on the implementation (e.g., in aerospace applications). This paper presents the architectural design of a low-latency bit-serial 1-Dimensional Wavelet Transform Processor.