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1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon最新文献

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Quick generation of temporal power waveforms for RT-level hard macros 快速生成时间功率波形的rt级硬宏
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630276
L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi
{"title":"Quick generation of temporal power waveforms for RT-level hard macros","authors":"L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi","doi":"10.1109/ICISS.1997.630276","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630276","url":null,"abstract":"Power characterization of complex macros is essential to enable accurate RT-level power estimation. Existing characterization procedures focus on the average value of power. In this paper, we take a fresh look at this problem. We propose a fast, yet accurate technique to determine a time-dependent power model, i.e., a temporal power waveform, which is able to fully characterize the power behavior of a hard macro in response to a realistic input stream consisting of typical usage patterns. Our approach is simulation-based, and resorts to a mix of high-level, fast cycle-based simulation with low-level, slow accurate simulation of the long set of input patterns. Results are extremely satisfactory, since the average error between the power waveforms generated by our tool and the exact ones is always within 1%, while the reduction in the execution time ranges between one and two orders of magnitude.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"65 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128021585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Comparative analysis of sensing schemes for multilevel non-volatile memories 多电平非易失性存储器传感方案的比较分析
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630269
C. Calligaro, A. Manstretta, A. Pierin, G. Torelli
{"title":"Comparative analysis of sensing schemes for multilevel non-volatile memories","authors":"C. Calligaro, A. Manstretta, A. Pierin, G. Torelli","doi":"10.1109/ICISS.1997.630269","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630269","url":null,"abstract":"Reading multilevel non-volatile memories is a very demanding task. Three sensing techniques (the parallel scheme, the binary-serial scheme and the mixed parallel-serial scheme) are considered here. Their operation principles are described and a comparative evaluation in terms of both access time and circuit complexity is carried out. The parallel approach is the most suitable for 4-level-cell memories (2 bit per cell). The mixed approach seems to be the most attractive for a large number of programmable levels (at least 16 levels per cell). In this case, the sensing area overhead is limited to less than 1% of the memory array while access time penalty is less than 50%.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121948285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The challenges in achieving sub-100 nm MOSFETs 实现100纳米以下mosfet的挑战
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630246
A. Tasch
{"title":"The challenges in achieving sub-100 nm MOSFETs","authors":"A. Tasch","doi":"10.1109/ICISS.1997.630246","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630246","url":null,"abstract":"The continued scaling of the MOS transistor to smaller feature sizes has been the prime factor in the remarkable advancements in integrated circuits over the past 25-30 years. This is due to the fact that successively smaller devices have allowed continued rapid improvements in the level of integration and performance. While sub-100 nm MOSFETs have been built in the laboratory, it is by no means straightforward to extend MOSFETs below 100 nm such that continued notable (cost justified) improvements in integrated circuit performance, reliability, and manufacturability will be maintained. This talk focuses on the major challenges that are encountered in designing and building MOSFETs with sub 100 nm gate lengths. The requirements on the structure and its component parts are examined, and potential solutions are discussed. Solutions to some of the challenges and obstacles will require revolutionary approaches and tremendous research and development resources and talent.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122314384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Redundancy techniques for high-density DRAMs 高密度dram的冗余技术
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630243
M. Horiguchi
{"title":"Redundancy techniques for high-density DRAMs","authors":"M. Horiguchi","doi":"10.1109/ICISS.1997.630243","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630243","url":null,"abstract":"This paper describes the redundancy techniques for high-density DRAMs to solve the following two problems which arise with the increase in memory capacity: (1) the increase in memory-array division reduces the replacement flexibility between defective lines and spare lines; (2) the defects causing DC-characteristics faults, especially excessive standby current faults cannot be repaired with the conventional redundancy techniques. First, two approaches to solve the first problem are discussed: enhancing the replacement flexibility within the limits of intra-subarray replacement, and the introduction of inter-subarray replacement. Next, the recent proposals to solve the second problem are reported. The DC-characteristics faults are repaired through the modification of bitline precharge circuit or the subarray-replacement redundancy.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124226593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
RF MEMS for digitally-controlled front-end components 用于数字控制前端元件的RF MEMS
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630277
E. R. Brown
{"title":"RF MEMS for digitally-controlled front-end components","authors":"E. R. Brown","doi":"10.1109/ICISS.1997.630277","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630277","url":null,"abstract":"Summary form only given, as follows. In recent years the field of microelectromechanical systems (MEMS) has grown very fast and merged with many defense and commercial applications. Much of this activity has been driven by the ability of MEMS to miniaturize, reduce the cost, and improve the performance of transducers and actuators previously fabricated by hybrid techniques. These benefits have stemmed from the compatibility of MEMS with silicon-based microelectronics and surface micromachining. A recent development along these lines is RF MEMS which, broadly speaking, is a new class of passive devices (e.g., switches) and circuit components (e.g., tunable transmission lines) composed of or controlled by MEMS. The most investigated RF MEMS device has been the electrostatic switch, consisting of either a thin metallic cantilever, diaphragm, or some other form of membrane that when pulled down to a bottom electrode shorts or opens a high frequency transmission line. For example, working on the DARPA MAFET-3 Program, Texas Instruments has recently demonstrated a \"BowTIe\" switch having an on-state-insertion and return loss of 0.15 dB and -20 dB, respectively, at 20 GHz when fabricated across the center conductor of a coplanar waveguide. Other organizations in the DARPA Program are pursuing RF MEMS cantilevers for switchable antennas and filters (Hughes Research Labs), and quasioptical beam-steering grids (Rockwell and Northrop Grumman). In all of these applications, the RF MEMS is promising a major positive impact on performance and cost-a rare occurrence for any technology just entering the RF arena.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133386713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Optical interconnects for commodity silicon technologies 用于商用硅技术的光互连
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630261
A. Krishnamoorthy
{"title":"Optical interconnects for commodity silicon technologies","authors":"A. Krishnamoorthy","doi":"10.1109/ICISS.1997.630261","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630261","url":null,"abstract":"Summary form only given. The concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit now appears to be a reality. The development of such optoelectronic-VLSI technology and its compatibility with submicron CMOS technology, is discussed by the author.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126748052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low power based partitioning and binding technique for single chip application specific DSP architectures 一种针对特定DSP架构的单芯片应用的低功耗分区和绑定技术
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630280
R. V. Cherabuddi, M. Bayoumi
{"title":"A low power based partitioning and binding technique for single chip application specific DSP architectures","authors":"R. V. Cherabuddi, M. Bayoumi","doi":"10.1109/ICISS.1997.630280","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630280","url":null,"abstract":"In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimizing the switching activity on the functional units as well as the global buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for partitioning the given data flow graph describing the DSP algorithm. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Ethernet switching-the enabling technology of SOHO implementation 以太网交换——SOHO实现的使能技术
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630265
D. Chung
{"title":"Ethernet switching-the enabling technology of SOHO implementation","authors":"D. Chung","doi":"10.1109/ICISS.1997.630265","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630265","url":null,"abstract":"Ethernet switching is an important networking technology that breaks the bandwidth bottleneck in the LAN environment. This technology is being feverishly exploited for the implementation of Intranets in Corporate America. In the long term, Ethernet switching will be the enabling technology for SOHO (Small Office and Home Office) implementation in the 21st Century. An Ethernet switch implemented with the latest VLSI technology, offers the best performance at the lowest cost. In the next 25 years, the development of VLSI Ethernet switch chips should parallel to the development of microprocessors of the past three decades.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131976359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Smartcards: portable security 智能卡:便携安全
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630268
J. Thomasson, L. Baldi
{"title":"Smartcards: portable security","authors":"J. Thomasson, L. Baldi","doi":"10.1109/ICISS.1997.630268","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630268","url":null,"abstract":"Smartcards are one of the fastest growing market segments in the field of microelectronics, since they offer an easy way to implement secure transactions. In this paper we will consider the main characteristics of smartcards, with special regard to the ones used for secure transactions, and discuss the main market and technology trends.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123356425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fault tolerance of one-time programmable FPGAs with faulty routing resources 具有错误路由资源的一次性可编程fpga的容错性
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1997-10-08 DOI: 10.1109/ICISS.1997.630256
F. Meyer, Xiao-Tao Chen, J. Zhao, F. Lombardi
{"title":"Fault tolerance of one-time programmable FPGAs with faulty routing resources","authors":"F. Meyer, Xiao-Tao Chen, J. Zhao, F. Lombardi","doi":"10.1109/ICISS.1997.630256","DOIUrl":"https://doi.org/10.1109/ICISS.1997.630256","url":null,"abstract":"This paper presents a novel approach for fault tolerance of one-time programmable FPGAs by reassignment of routing resouces. As the underlying problem is NP-complete, a greedy algorithm is proposed to provide rapid, but suboptimal solutions. Due to the one-time programmable characteristic of the switches (commonly referred to as antifuses), only unused (fault-free) routing resources must be utilized for reassignment in a chip with a faulty interconnect. We specifically investigate whether reassignment could be accomplished without changing the global routing of any connections. A RC-tree model for the net delay is also presented; delay bounds are established to fully quantify the degradation due to the reassignment. Extensive simulation results are provided.","PeriodicalId":357602,"journal":{"name":"1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129603539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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