Test strategy sensitivity to floating gate fault parameter

Abstract

This paper studies the detectability of floating gate faults considering static voltage, dynamic voltage and static current strategies. It is shown that the behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters (polysilicon-to-bulk capacitance). It is shown that a floating gate fault can induce abnormal logic values, additional delays or increased static current (I/sub DDQ/). Consequently, any test strategy is able to detect floating gate faults, each one for a given range of the unpredictable parameter. It is then demonstrated that the fundamental criterion for test strategy efficiency evaluation is the consideration of the corresponding intervals.