A parallel DSP testbed with a heterogeneous and reconfigurable network fabric

Abstract

A testbed for investigation of heterogeneous and reconfigurable data network fabrics supporting a parallel DSP computational accelerator is described. The DSP processors are large-grained processors (Analog Devices SHARC DSPs), with a variety of parallel DSP array architectures possible. The network fabric is intended to be reconfigurable (within a rich but necessarily limited set of structures) to adapt to the needs of a sequence of image processing algorithms being executed (e.g., in a medical image processing environment). The testbed will exploit conventional FPGA components to provide reconfigurable network structures and will exploit commercial high-speed interconnect components emerging for applications such as board-to-board applications. As a computational accelerator, the testbed is intended to be controlled by a host processor, with the host processor cooperating in the definition of the changes in the structure of the network structure as execution of a sequence of image processing algorithms proceeds.