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2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting最新文献

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Notice of Violation of IEEE Publication PrinciplesA Zero-Second-IF SiGe BiCMOS Satellite Radio Tuner Using a Single PLL for Both RF and IF LO Generation and a Replica Ring-VCO Calibrated IF Filter 一个零秒中频SiGe BiCMOS卫星无线电调谐器，使用单个锁相环产生RF和中频LO，并使用复制环vco校准中频滤波器
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351825
A. Maxim, M. Gheorge, C. Turinici
{"title":"Notice of Violation of IEEE Publication PrinciplesA Zero-Second-IF SiGe BiCMOS Satellite Radio Tuner Using a Single PLL for Both RF and IF LO Generation and a Replica Ring-VCO Calibrated IF Filter","authors":"A. Maxim, M. Gheorge, C. Turinici","doi":"10.1109/BIPOL.2007.4351825","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351825","url":null,"abstract":"A fully-integrated tuner for digital satellite audio radio applications using a second-zero-IF dual conversion architecture was realized in a 0.2 mum SiGe BiCMOS technology. An autonomous RF-AGC and a channel decoder IC controlled IF-AGC were used to optimize the signal path gain for a wide range of input signal levels. A single PLL drives both RF and IF mixers, resulting in a smaller die area and lower power dissipation. Down-converting the signal to baseband further reduces tuner's power due to a lower required ADC sampling frequency and resolution. Providing a digital baseband I/Q output allows the implementation of the channel decode IC in a standard digital CMOS process, reducing the overall receiver cost. SDARS tuner performance includes: 5 dB noise figure, 55 dB image rejection, -100 dBm input sensitivity, +15 dBm IIP3 at min gain, 40/60d B RF/IF AGC range, 120 mA current consumption from a 3.3 V supply and 15 mm2 die area.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116949486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
60GHz LNA and 15GHz VCO Design for Use in Broadband Millimeter-Wave WPAN System 用于宽带毫米波WPAN系统的60GHz LNA和15GHz VCO设计
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351871
K. To, P. Welch, D. Scheitlin, B. Brown, D. Hammock, M. Tutt, D. Morgan, S. Braithwaite, J. John, J. Kirchgessner, W.M. Huang
{"title":"60GHz LNA and 15GHz VCO Design for Use in Broadband Millimeter-Wave WPAN System","authors":"K. To, P. Welch, D. Scheitlin, B. Brown, D. Hammock, M. Tutt, D. Morgan, S. Braithwaite, J. John, J. Kirchgessner, W.M. Huang","doi":"10.1109/BIPOL.2007.4351871","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351871","url":null,"abstract":"This paper presents a 60 GHz LNA and a 15 GHz VCO with wide frequency range for Millimeter WPAN operating from 57-64 GHz. Using a cost-effective SiGe BiCMOS technology with ft and fmax of 200 GHz and 300 GHz respectively, the LNA demonstrates good matching and a gain of more than 20 dB with excellent flatness (less than 1.2 dB) from SSGHz to 65 GHz. The 15 GHz VCO, which is used to generate the 60 GHz LO signal, exhibits high output power of above 2 dBm with tuning range of 20%. This translates to a frequency range of 53 GHz to 66 GHz.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131866998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact of layout and process on RF and analog performances of 3D damascene MIM capacitors 布局和工艺对三维大马士革MIM电容器射频和模拟性能的影响
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351879
S. Crémer, N. Segura, P. Joubin, M. Marin, M. Thomas, C. Richard, S. Boret, D. Benoit, S. Bruyère
{"title":"Impact of layout and process on RF and analog performances of 3D damascene MIM capacitors","authors":"S. Crémer, N. Segura, P. Joubin, M. Marin, M. Thomas, C. Richard, S. Boret, D. Benoit, S. Bruyère","doi":"10.1109/BIPOL.2007.4351879","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351879","url":null,"abstract":"RF and analog designs require high performances MIM capacitors. In order to continue the downscaling of MIM devices, we proposed and integrated a 3D damascene MIM capacitor using Si3N4 dielectric in the copper back-end of a 0.13 mum BICMOS technology. Layout and process have been recently optimized to reach excellent reliability performances while keeping very good RF performances.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133230544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Highly Efficient Class E SiGe Power Amplifier Design for Wireless Sensor Network Applications 无线传感器网络应用的高效E级SiGe功率放大器设计
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351859
D. Lie, J. Lopez, J. Rowland
{"title":"Highly Efficient Class E SiGe Power Amplifier Design for Wireless Sensor Network Applications","authors":"D. Lie, J. Lopez, J. Rowland","doi":"10.1109/BIPOL.2007.4351859","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351859","url":null,"abstract":"This paper discusses the design of highly efficient and monolithic medium-power RF class E SiGe power amplifiers (PAs) in IBM 7HP SiGe BiCMOS technology at both 900 MHz and 2.4 GHz for wireless sensor applications. Without needing off-chip on-board matching, we achieved high power-added-efficiency (PAE) for the single-stage class E SiGe PAs at ~70% (900 MHz) and ~60% (2.4 GHz), respectively. Using large number of downbonds at the emitter node of the PA, optimal device sizing and layout, and careful circuit design with bondwire tank inductors, maximum PAE of 62% at 2.4 GHz is obtained, which performance rivals that of commercially-available III-V PA modules. Taking advantages of the higher output power with breakdown robustness and the excellent PAE for SiGe PAs vs. CMOS PAs, one can not only shrink the battery size and therefore sensor volume, but also reduce the number of nodes required in a wireless sensor network to bring down system cost and simplify data fusion. With improved understanding of on-chip PA loss mechanisms, it is likely that we can push these high-efficient SiGe PAs into higher frequencies of operation (say 10 GHz) to utilize smaller antenna size, enabling new and exciting wireless sensor network applications.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127585182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Ultra-low Voltage Analog Integrated Circuits for nanoscale CMOS 纳米级CMOS的超低电压模拟集成电路
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351856
P. Kinget
{"title":"Ultra-low Voltage Analog Integrated Circuits for nanoscale CMOS","authors":"P. Kinget","doi":"10.1109/BIPOL.2007.4351856","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351856","url":null,"abstract":"We will review design challenges and opportunities for ultra-low voltage analog and RF integrated circuits in nanoscale CMOS technologies.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"48 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131499995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
New Method for Oxide Capacitance Extraction 氧化物电容萃取新方法
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351866
C. Raya, T. Schwartzmann, P. Chevalier, F. Pourchon, D. Céli, T. Zimmer
{"title":"New Method for Oxide Capacitance Extraction","authors":"C. Raya, T. Schwartzmann, P. Chevalier, F. Pourchon, D. Céli, T. Zimmer","doi":"10.1109/BIPOL.2007.4351866","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351866","url":null,"abstract":"Based on different geometries of bipolar transistors, a new scalable method to determine the parasitic capacitances is presented. The total capacitance measured from cold S parameters could be split in an area junction capacitance, a peripheral junction capacitance and a constant oxide contribution. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS technology, and results are discussed.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123291588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New electro-thermal modeling tools for automotive power circuits design optimization 用于汽车电源电路设计优化的新型电热建模工具
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351844
W. Habra, P. Tounsi, P. Dupuy, J. Dorkel, F. Madrid
{"title":"New electro-thermal modeling tools for automotive power circuits design optimization","authors":"W. Habra, P. Tounsi, P. Dupuy, J. Dorkel, F. Madrid","doi":"10.1109/BIPOL.2007.4351844","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351844","url":null,"abstract":"An innovative and accurate compact thermal model (CTM) extraction methodology for multi-chip automotive power electronics systems is proposed. Compared to the existing methods, e.g. the Delphi method, the number of needed 3D thermal simulations is significantly reduced and transient electro-thermal coupling is easily achieved. An example of experimental CTM extraction procedure is provided.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120956914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.35 μm SiGe BiCMOS technology for power amplifier applications 用于功率放大器应用的0.35 μm SiGe BiCMOS技术
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351868
A. Joseph, Qizhi Z. Liu, W. Hodge, P. Gray, K. Stein, R. Previti-Kelly, P. Lindgren, E. Gebreselasie, B. Voegeli, P. Candra, D. Hershberger, R. Malladi, Ping-Chuan Wang, K. Watson, Z. He, J. Dunn
{"title":"A 0.35 μm SiGe BiCMOS technology for power amplifier applications","authors":"A. Joseph, Qizhi Z. Liu, W. Hodge, P. Gray, K. Stein, R. Previti-Kelly, P. Lindgren, E. Gebreselasie, B. Voegeli, P. Candra, D. Hershberger, R. Malladi, Ping-Chuan Wang, K. Watson, Z. He, J. Dunn","doi":"10.1109/BIPOL.2007.4351868","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351868","url":null,"abstract":"In this paper we introduce, a state-of-the-art SiGe BiCMOS power amplifier technology that features two NPNs with 40 GHz / 6.0 V & 27 GHz / 8.5 V (fT - BVceo) respectively, a novel low inductance metal ground through-silicon-via (TSV), integrated on a low-cost 0.35 μm lithography node with 3.3 V / 5.0 V dual-gate CMOS technology and high-quality passives on a 50 Ω.cm substrate.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126293635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 10V complementary SiGe BiCMOS foundry process for high-speed and high-voltage analog applications 用于高速和高压模拟应用的10V互补SiGe BiCMOS铸造工艺
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351834
T. Tominari, M. Miura, H. Shimamoto, M. Arai, Y. Yoshida, H. Sato, T. Aoki, H. Nonami, S. Wada, H. Hosoe, K. Washio, T. Hashimoto
{"title":"A 10V complementary SiGe BiCMOS foundry process for high-speed and high-voltage analog applications","authors":"T. Tominari, M. Miura, H. Shimamoto, M. Arai, Y. Yoshida, H. Sato, T. Aoki, H. Nonami, S. Wada, H. Hosoe, K. Washio, T. Hashimoto","doi":"10.1109/BIPOL.2007.4351834","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351834","url":null,"abstract":"A manufacturable 10V-BVcc/15GHz-fr complementary SiGe BiCMOS foundry process was developed for high-performance multi-media applications. A novel SiGe profile with a forward/backward stepped Ge profile and controllable emitter interface layer improved the SiGe PNP's FOM to 620 GHz ldrV.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125722453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Assessing the High-Temperature Capabilities of SiGe HBTs Fabricated on CMOS-compatible Thin-film SOI 基于cmos兼容薄膜SOI的SiGe hbt高温性能评估
2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 2007-10-22 DOI: 10.1109/BIPOL.2007.4351877
M. Bellini, J. Cressler, Jin Cai
{"title":"Assessing the High-Temperature Capabilities of SiGe HBTs Fabricated on CMOS-compatible Thin-film SOI","authors":"M. Bellini, J. Cressler, Jin Cai","doi":"10.1109/BIPOL.2007.4351877","DOIUrl":"https://doi.org/10.1109/BIPOL.2007.4351877","url":null,"abstract":"We quantitatively assess, for the first time, the capabilities of SiGe HBTs fabricated on thin-film SOI for emerging high-temperature circuit applications. The dc and ac performance of both fully-depleted and partially-depleted SiGe HBTs-on-SOI are measured up to a temperature of 330degC (for dc) and 200degC (for ac). Gummel characteristics, current gain, and output characteristics are reported. M-l is used to investigate how collector doping affects the device behavior at high temperatures. We demonstrate that despite the harsh conditions imposed by high-temperature operation, SiGe HBTs-on-SOI maintain adequate performance for many applications for temperatures in the 200-300degC range.","PeriodicalId":356606,"journal":{"name":"2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132378858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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