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ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)最新文献

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A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS 一个230mV-950mV 2.8Tbps/W统一SHA256/SM3安全哈希硬件加速器，14nm三栅极CMOS
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494257
Vikram B. Suresh, Sudhir K. Satpathy, S. Mathew, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, R. Krishnamurthy
{"title":"A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS","authors":"Vikram B. Suresh, Sudhir K. Satpathy, S. Mathew, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, R. Krishnamurthy","doi":"10.1109/ESSCIRC.2018.8494257","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494257","url":null,"abstract":"A unified SHA256/SM3 secure hashing hardware accelerator for cross-geo authentication is fabricated in 14nm tri-gate CMOS, with a throughput of 9.5/8.3Gbps respectively measured at 0.75V, 25°C. Message digest pre-addition, with mode-multiplexed digest/scheduler completion adders and distributed final hash computation reduces critical path delay by 14% and accelerator area by 48%, resulting in a compact layout of 5992µm2. 2/4-way parallel message scheduler enables 0.5/0.25× frequency scaling at iso-hash throughput enabling 35/62% scheduler power reduction. Robust sub-threshold voltage operation down to 230mV enables a peak energy-efficiency of 2.8Tbps/W measured at 300mV.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114301389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS 一个125 MS/s 10.4 ENOB 10.1 fJ/反步多比较器SAR ADC，具有比较器噪声缩放
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494253
Shaolong Liu, J. Paramesh, L. Pileggi, T. Rabuske, Jorge Fernandcs
{"title":"A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS","authors":"Shaolong Liu, J. Paramesh, L. Pileggi, T. Rabuske, Jorge Fernandcs","doi":"10.1109/ESSCIRC.2018.8494253","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494253","url":null,"abstract":"Traditional SAR ADC employs a single comparator for all comparisons in the binary-search (BS) algorithm. Since the noise present in each comparison contributes differently to the overall ADC noise, that approach generally leads to sub-optimal performance in terms of the noise/power trade-off, as the comparator is sized for the worst-case LSB comparison. This paper presents a multi-comparator SAR ADC featuring noise scaling on the comparators. Since the comparator noise impact increases exponentially from MSB to LSB, we exponentially scale the comparators noise voltage upward from the LSB (which requires low noise) to the MSB for saving power consumption. Furthermore, the MSB comparators are designed for higher bandwidth (and thus worse noise) compared to the LSB comparators to facilitate high conversion speed. These techniques are demonstrated by a single channel, 12-bit SAR design with 5 different comparators. A background calibration technique is proposed to alleviate comparator offset mismatch. The 65 nm CMOS ADC runs up to 125MS/s achieving SNDR/SFDR of 64.4/75.1dB above Nyquist frequency and consumes 1.7mW from 1.2 V supply and has an FoM of 10.1 fJ/conv-step. To our best knowledge, this is the first reported single channel> 10 ENOB SAR ADC to achieve> 100 MS/s conversion speed.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128417285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 36V 48MHz JFET-Input Bipolar Operational Amplifier with 150µV Maximum Offset and Overload Supply Current Control 一个36V 48MHz jfet输入双极运算放大器，最大失调150µV和过载供电电流控制
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494262
M. Snoeij
{"title":"A 36V 48MHz JFET-Input Bipolar Operational Amplifier with 150µV Maximum Offset and Overload Supply Current Control","authors":"M. Snoeij","doi":"10.1109/ESSCIRC.2018.8494262","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494262","url":null,"abstract":"This paper presents a 36V JFET -input bipolar operational amplifier with an unprecedented combination of DC precision (150µV offset, 1.5 µV/°C drift) and high speed (48MHz GBW, 160V/µs slew-rate). The high slew-rate is obtained using the well-known slew-boosting method. However, conventional slew-boost circuits can cause excessive power consumption when the amplifier inputs are overloaded and the output hits the rail. Therefore, a dedicated protection circuit was added that detects such an overload condition, and limits power consumption in this condition.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126909745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Generating the Next Wave of Custom Silicon 产生下一波定制硅
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494310
B. Nikolić, E. Alon, K. Asanović
{"title":"Generating the Next Wave of Custom Silicon","authors":"B. Nikolić, E. Alon, K. Asanović","doi":"10.1109/ESSCIRC.2018.8494310","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494310","url":null,"abstract":"Tidal waves in computing and communications have traditionally fueled the growth of the semiconductor industry. Mainframes have been replaced by personal computers, followed by the proliferation of mobile telephones, each resulting in dramatic increases in volumes of units shipped. The upcoming generation of computing does not have one clear product to drive the industry; Rather a diversity of emerging applications are based on the interaction between edge devices and the cloud. Supporting differentiation amongst diverse products requires specialization of integrated circuits, which in turn requires a paradigm shift in the design of custom silicon. This paper outlines a vision to dramatically increase design reuse by focusing on developing digital and analog generators rather than specific instances of functional modules. The use of the open and extensible RISC-V instruction-set architecture enables customization with reduced software cost. Open-source chip generators amortize the design and verification costs across many instances. Emulation of multi-processor systems running realistic workloads on public clouds validates design decisions at a dramatically reduced cost. The methodology is illustrated by the design of a complex system-on-a-chip.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124174638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 28nm-CMOS 100MHz 1mW 12dBm-IIP3 4th-Order Flipped-Source-Follower Analog Filter 一个28nm-CMOS 100MHz 1mW 12dBm-IIP3四阶翻转源跟随器模拟滤波器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494263
F. Fary, M. Matteis, T. Vergine, A. Baschirotto
{"title":"A 28nm-CMOS 100MHz 1mW 12dBm-IIP3 4th-Order Flipped-Source-Follower Analog Filter","authors":"F. Fary, M. Matteis, T. Vergine, A. Baschirotto","doi":"10.1109/ESSCIRC.2018.8494263","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494263","url":null,"abstract":"This paper presents the design in 28nm-CMOS technology of a 100MHz–3dB-bandwidth analog filter based on the Flipped-Source-Follower stage. The filter performs large inband linearity thanks to a proper local loop, whose optimization at design level can be shielded from the Source-Follower input transistor that dominates the noise power. This enables better noise/linearity trade-off vs. power efficiency comparing with the Source-Follower filters state-of-the-art. The circuit implements a 4th-order Butterworth low-pass transfer function and achieves 12.5dBm IIP3 at 968µW power consumption from a single 1V supply voltage. The in-band noise power spectral density is 8nV/√Hz resulting in an in-band integrated noise of 98µVRMS. Total Harmonic Distortion at 20 MHz is −40dB with −6dBm single tone output signal, resulting in 64dB Dynamic Range. The achieved Figure-of-Merit (160.5 J−1) compares very favorably with the state-of-the-art.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128121393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.5 V, 650 pW, 0.031%/V Line Regulation Subthreshold Voltage Reference 0.5 V, 650pw, 0.031%/V线路调节亚阈值电压基准
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494332
Yuwei Wang, Ruizhi Zhang, Quan Sun, Hong Zhang
{"title":"A 0.5 V, 650 pW, 0.031%/V Line Regulation Subthreshold Voltage Reference","authors":"Yuwei Wang, Ruizhi Zhang, Quan Sun, Hong Zhang","doi":"10.1109/ESSCIRC.2018.8494332","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494332","url":null,"abstract":"This paper presents a self-biased subthreshold voltage reference using the VTH difference between a thick-oxide MOS and a thin-oxide MOS to compensate the thermal voltage's temperature coefficient (TC). Based on theoretical analysis, the thick-oxide MOS's drain is selected as the output with optimized bias current, resulting in a robust voltage reference insensitive to process and supply variations. Fabricated in a 0.18-µm 1.8 V/ 3.3 V CMOS process, the proposed circuit achieves a line regulation of 0.031%/V under a supply voltage range from 0.5 to 2.2 V and a PSRR of −61.5 dB at 100 Hz before trimming. Under 25°C and a 1.2-V supply voltage, the average output voltage before trimming for 27 samples is 211.46 mV with standard deviation of only 0.64 mV (a/µ = 0.3 %). The average TCs before and after trimming are 152.8 and 11.4 ppm/°C, respectively, with total power consumption of 650 pW at 0.5 V and active area of 0.0012 mm2.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"7 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit A 0.78-µW 96-Ch。集成了纳瓦功率管理单元的深度亚vt神经脉冲处理器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494273
Jiangyi Li, P. K. Chundi, S. Kim, Zhewei Jiang, Minhao Yang, Joonseong Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok
{"title":"A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit","authors":"Jiangyi Li, P. K. Chundi, S. Kim, Zhewei Jiang, Minhao Yang, Joonseong Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok","doi":"10.1109/ESSCIRC.2018.8494273","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494273","url":null,"abstract":"We present a sub-µW Neural Spike Processor integrated with a Power Management Unit (PMU) for on-implant processing in motor intention decoding, demonstrating: (i) among the highest level of integration including spike detection, feature extraction, sorting, the first half of decoding, which reduces wireless data rate by more than 4 orders of magnitude; (ii) on-chip PMU integration enabling the system directly powered by harvesters; (iii) the lowest power dissipation of 0.78µW for 96 channels, 21x lower than the prior art at a comparable/better accuracy.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123166480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS 基于65纳米LP CMOS的0.02 mm2 9位100 ms /s电荷注入电池SAR-ADC
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494339
Marcel Runge, Dario Schmock, P. Scholz, Georg Böck, F. Gerfers
{"title":"A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS","authors":"Marcel Runge, Dario Schmock, P. Scholz, Georg Böck, F. Gerfers","doi":"10.1109/ESSCIRC.2018.8494339","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494339","url":null,"abstract":"This paper presents the first published 9 bit resolution charge-injection cell based area-efficient SAR-ADC (ciSAR). The ciSAR employs both, a charge pump technique as well as a charge balancing switching scheme during binary search. Herewith, the ciSAR achieves a maximum input differential swing of 1.4 V with 10 bit linearity up to the second Nyquist zone. Additionally, the non-linear comparator input capacitance is isolated from the track and hold function for linearity improvements during the top-plate sampling operation. The ADC is reference-free and features an intrinsic 4.5 dB gain tuning range with only minor SNDR and SFDR variations of less than 2 dB. Implemented in a 65nm LP CMOS process, the ADC reveals 7.5bit ENOB and 62 dBc SFDR up to second Nyquist zone. With an area of only 0.02mm2 and an aspect ratio of 1:4, the ciSAR with 451 MHz effective resolution bandwidth enables highly parallel sensor readout systems.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121915919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier 基于注入锁定功率放大器的低功率QPSK发射机
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494300
Zexi Ji, Saba Zargham, A. Liscidini
{"title":"Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier","authors":"Zexi Ji, Saba Zargham, A. Liscidini","doi":"10.1109/ESSCIRC.2018.8494300","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494300","url":null,"abstract":"An injection-locked frequency divider was used as a quadrature phase-shift keying (QPSK) modulator by exploiting the property that a polarity flip of the injected signal results in a phase shift of 90 degrees at the output. Furthermore, the power amplifier was integrated with the divider by adding a transformer to couple to the antenna. Combining these two ideas resulted in a high-efficiency, high-bandwidth QPSK transmitter, capable of operating at up to 120 Mbit/s and delivering 1.3 m W output power with a system efficiency of 38 %.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127143499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver 一个0.85mm2的嵌入式T/R开关BLE收发器，2.6mW全无源谐波抑制发射器和2.3mW混合环路接收器
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2018-09-01 DOI: 10.1109/ESSCIRC.2018.8494276
Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, T. Kaneko, Rui Wu, W. Deng, K. Okada
{"title":"A 0.85mm2 BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver","authors":"Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, T. Kaneko, Rui Wu, W. Deng, K. Okada","doi":"10.1109/ESSCIRC.2018.8494276","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2018.8494276","url":null,"abstract":"This paper presents a miniaturized Bluetooth Low-Energy transceiver for short-range IoT applications in 65-nm CMOS. A T/R switch embedded with transmitter harmonic-suppression and on-chip impedance matching is proposed. The BLE transceiver delivers −6dBm output while consuming 2.6mW. 18.5% TX efficiency is achieved at OdBm output power. A −94dBm receiver sensitivity is achieved with 2.3mW receiver power consumption. Thanks to the T/R switch embedded with harmonic suppression, −56dBc of 2nd-order harmonic distortion (HD2) and −48dBc of 3rd-order harmonic distortion (HD3) suppressions are achieved. The fabricated BLE transceiver occupies 0.85mm2 active area. This transceiver satisfies the BLE radio specification without the need for external filters, that enables minimum size modules and short time to market.","PeriodicalId":355210,"journal":{"name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130690027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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